The boot ROMs of the socfpga platform limit the size of the SPL to copy to less than the available SRAM. (See "Intel SoC FPGA Embedded Development Suite User Guide")
According to this document, Cyclone V and Arria V allow 60KB maximum while Arria 10 allows 200KB. In both cases, this is less than CONFIG_SYS_INIT_RAM_SIZE.
Signed-off-by: Simon Goldschmidt sgoldschmidt@de.pepperl-fuchs.com --- include/configs/socfpga_common.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4de2aa7929..bf7014064a 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -31,9 +31,12 @@ #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0xF000 /* 60KB */ + #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ +#define CONFIG_SPL_MAX_SIZE 0x32000 /* 200KB */ #endif #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) @@ -254,7 +257,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * 0xFFFF_FF00 ...... End of SRAM */ #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
/* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT