From: Marcel Ziswiler marcel.ziswiler@toradex.com
On popular request make the display driver from T20 work on T30 as well. Turned out to be quite straight forward. However a few notes about some things encountered during porting: Of course the T30 device tree was completely missing host1x as well as PWM support but it turns out this can simply be copied from T20. The only trouble compiling the Tegra video driver for T30 had to do with some hard-coded PWM pin muxing for T20 which is quite ugly anyway. On T30 this gets handled by a board specific complete pin muxing table. The older Chromium U-Boot 2011.06 which to my knowledge was the only prior attempt at enabling a display driver for T30 for whatever reason got some clocking stuff mixed up. Turns out at least for a single display controller T20 and T30 can be clocked quite similar. Enjoy.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # ASUS TF T30 Tested-by: Jonas Schwöbel jonasschwoebel@yahoo.de # Surface RT T30 Tested-by: Svyatoslav Ryhel clamor95@gmail.com # LG P895 T30 Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com Signed-off-by: Svyatoslav Ryhel clamor95@gmail.com --- arch/arm/dts/tegra30-u-boot.dtsi | 9 +++++++ arch/arm/include/asm/arch-tegra30/display.h | 28 +++++++++++++++++++++ arch/arm/include/asm/arch-tegra30/pwm.h | 13 ++++++++++ drivers/video/tegra.c | 10 ++++++-- 4 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra30/display.h create mode 100644 arch/arm/include/asm/arch-tegra30/pwm.h
diff --git a/arch/arm/dts/tegra30-u-boot.dtsi b/arch/arm/dts/tegra30-u-boot.dtsi index 7c11972552..cf17fa803b 100644 --- a/arch/arm/dts/tegra30-u-boot.dtsi +++ b/arch/arm/dts/tegra30-u-boot.dtsi @@ -1,3 +1,12 @@ #include <config.h>
#include "tegra-u-boot.dtsi" + +/ { + host1x@50000000 { + u-boot,dm-pre-reloc; + dc@54200000 { + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-tegra30/display.h b/arch/arm/include/asm/arch-tegra30/display.h new file mode 100644 index 0000000000..9411525799 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra30/display.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * NVIDIA Corporation <www.nvidia.com> + */ + +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H +#define __ASM_ARCH_TEGRA_DISPLAY_H + +#include <asm/arch-tegra/dc.h> + +/* This holds information about a window which can be displayed */ +struct disp_ctl_win { + enum win_color_depth_id fmt; /* Color depth/format */ + unsigned int bpp; /* Bits per pixel */ + phys_addr_t phys_addr; /* Physical address in memory */ + unsigned int x; /* Horizontal address offset (bytes) */ + unsigned int y; /* Veritical address offset (bytes) */ + unsigned int w; /* Width of source window */ + unsigned int h; /* Height of source window */ + unsigned int stride; /* Number of bytes per line */ + unsigned int out_x; /* Left edge of output window (col) */ + unsigned int out_y; /* Top edge of output window (row) */ + unsigned int out_w; /* Width of output window in pixels */ + unsigned int out_h; /* Height of output window in pixels */ +}; + +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra30/pwm.h b/arch/arm/include/asm/arch-tegra30/pwm.h new file mode 100644 index 0000000000..c314e2b5ad --- /dev/null +++ b/arch/arm/include/asm/arch-tegra30/pwm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Tegra pulse width frequency modulator definitions + * + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __ASM_ARCH_TEGRA30_PWM_H +#define __ASM_ARCH_TEGRA30_PWM_H + +#include <asm/arch-tegra/pwm.h> + +#endif /* __ASM_ARCH_TEGRA30_PWM_H */ diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 3f9fcd0403..5e3f6bf029 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -40,8 +40,8 @@ struct tegra_lcd_priv {
enum { /* Maximum LCD size we support */ - LCD_MAX_WIDTH = 1366, - LCD_MAX_HEIGHT = 768, + LCD_MAX_WIDTH = 1920, + LCD_MAX_HEIGHT = 1200, LCD_MAX_LOG2_BPP = VIDEO_BPP16, };
@@ -307,14 +307,19 @@ static int tegra_lcd_probe(struct udevice *dev) int ret;
/* Initialize the Tegra display controller */ +#ifdef CONFIG_TEGRA20 funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); +#endif + if (tegra_display_probe(blob, priv, (void *)plat->base)) { printf("%s: Failed to probe display driver\n", __func__); return -1; }
+#ifdef CONFIG_TEGRA20 pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); pinmux_tristate_disable(PMUX_PINGRP_GPU); +#endif
ret = panel_enable_backlight(priv->panel); if (ret) { @@ -414,6 +419,7 @@ static const struct video_ops tegra_lcd_ops = {
static const struct udevice_id tegra_lcd_ids[] = { { .compatible = "nvidia,tegra20-dc" }, + { .compatible = "nvidia,tegra30-dc" }, { } };