7 Mar
2014
7 Mar
'14
11:56 p.m.
On 02/26/2014 02:36 AM, Shaveta Leekha wrote:
- SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz
- Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration
Signed-off-by: Shaveta Leekha shaveta@freescale.com
Applied to u-boot-mpc85xx/master. Thanks.
York