17 Feb
2015
17 Feb
'15
9:24 p.m.
On Mon, Feb 16, 2015 at 10:15:55AM +0530, Lokesh Vutla wrote:
From: Angela Stegmaier angelabaker@ti.com
DDR3 timing and latency paramenters were not configured correctly for 666MHz. Fixing the timing and latency values according to Data sheet. This fixes the random crashes seen on DRA72-evm.
Signed-off-by: Angela Stegmaier angelabaker@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Applied to u-boot/master, thanks!
--
Tom