8 Mar
2021
8 Mar
'21
8:59 a.m.
On Sun, Mar 7, 2021 at 1:25 AM Jernej Skrabec jernej.skrabec@siol.net wrote:
Video driver currently manages clocks and resets by directly writing to registers. This is already a bit messy because each SoC has some specifics. It's much better to implement proper clock and reset driver which takes information from device tree file.
Note that this driver is not perfect yet. It still sets PLL and parent by hand. Sunxi clock framework still doesn't know how to set parents or rates. However, this is already big step in right direction.
Cc: Lukasz Majewski lukma@denx.de Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net
Reviewed-by: Jagan Teki jagan@amarulasolutions.com