Stefan Roese wrote:
On Thursday 24 April 2008, Ayman M. El-Khashab wrote:
So maybe I need to clarify some more. The PPC460 data sheet is not too clear on this yet. However, here are my thoughts on this. Lets just take the simple case as an example. We have a plurality of 460s where a single one is the master. Between the master and all the slaves is a PCI bridge. The slaves are hardwired to boot from pci bus memory -- according to the datasheet that is at a fixed address. So there does not appear to be any need to do anything to the slave upon power up. Now the master boots and then allocates a chunk of contiguous memory using a kernel driver or whatever is needed. The image is just whatever the flash image would normally contain (uboot + kernel + rootfs). The address of that chunk is then given to the pci bridge so that it can perform inbound translation from the address that the PPC slaves will use to the address where the image is physically located. Then the slaves are taken out of reset and begin reading "flash" across the pci bus which really goes through the bridge and is mapped to the DRAM on the master (or I guess it could be the flash on the master, but DRAM seemed easier since it is already running).
Ok, so how many holes does this approach have?
Sounds quite reasonable. The only thing I'm unsure here is the size of the PCI windows that is mapped upon PCI booting.
Thanks for all your help ...
I thought the answer to both questions was in footnote 3 on page 8 of the data sheet. At least that was my interpretation of the following statement: "3. When the optional boot from PCI Memory is selected, the PCI Boot ROM address space begins at 0000 000C FF00 0000 (16 MB)."
I interpreted that to mean the address was not something that needed to be configured in any sort of bar register and that the address it fetched was fixed. So the only thing that was required was to configure the inbound translation on the bridge.
- ame