Hi Tom,
I suspect that this might be related to the general problem on these part families where SPL isn't as fast as we expect it to be, perhaps cache related.
I did a bit of digging around following this line of thought and found an old discussion on the mailing list (http://lists.denx.de/pipermail/u-boot/2013-June/156949.html) regarding someone who had a very similar problem with SPL/Falcon and NAND flash.
I have emailed Bas van den Berg to see if he is willing to share his final implementation as adding the code that adds the SRAM to the MMU and enables the caches to the end of am33xx_spl_board_init() hangs within the enable_caches() function.
Unfortunately this getting well out of my comfort zone with the ARM cores and so I'm not sure where to go next and how to debug it further.
Regards,
Andy.