From: Robert Delien robert@delien.nl
This patch makes a small correction to the mx28evk board pin configuration.
1. The Debug UART (DUART) SPIO pins should be operating in the 3v3 domain, not the 1v8 domain, because the connected MX3222 level- shifter operates in the 3v3 domain too.
2. The SSP0 card detect pin doesn't require a drive strength configuration because it's an input. Configuring it as all other SSP0 pins will do here. A SSP0 clock signal drive strength of 12mA is much too loud. The FSL supplied U-Boot uses the same drive strength for the clock as it does for all ohter SSP0 signals. The Write-protect input is configured the same, yet more explicitly specified.
3. Pin configuration for SSP1 has been added for MMC1. Because the use of MMC1 is mutually exclusive with the use of NAND flash, this is only active when NAND flash is not configured in.
4. Pin configuration for NAND flash has been added.
Robert Delien (4): Debug UART pins configured to 3v3, instead of 1v8 Correction to SSP0 drive strengths SSP1 pins configured for MMC1 Added NAND flash pin configuration
board/freescale/mx28evk/iomux.c | 71 ++++++++++++++++++++++++++++++++------ 1 files changed, 59 insertions(+), 12 deletions(-)