TNETV107X is an ARM1176 SoC with a bunch on on-chip integrated peripherals. As suggested by Tom, this patch embeds the "ARM1176: Coexist with other ARM1176 platforms" patch posted on the list earlier.
At this point, I am faced with a bit of convoluted nastiness, and I would very much appreciate feedback and ideas on some of the issues detailed here.
This SOC needs a bit of an unusual boot up initialization process. The ROM code initializes the SOC's PLLs, DDR and NAND to "conservative" values before loading up u-boot into DDR and executing it. Subsequently, based on configuration read from eFUSE (and possibly board tie-offs and/or environment variables), the on-board power management device and PLL need to be reprogrammed to run at a different voltage and frequency respectively.
This is done as follows:
1. Relocate necessary code and data to on-chip SRAM 2. Switch to SRAM stack and branch to init code in SRAM 3. Get devices into a "safe" state: 3(a) Place the DDR SDRAM in self-refresh mode - From this point on main memory should _not_ be accessed 3(b) Shutdown other devices - none for now 4. Program the power management IC to the required voltage 5. Reprogram PLL to the required frequency and adjust the rest of the clock tree as necessary 6. Restore devices: 6(a) Recalculate memory timing and reprogram the memory controller 6(b) Recalculate other clocks as necessary (e.g. UART) 6(c) Reactivate DDR SDRAM by taking it out of self-refresh. 7. Return to u-boot in DDR 8. ...breathe...
This whole thing is pretty non-trivial, and hand coding this entire process in position independent assembly would result in a maintenance nightmare.
For this reason, I have implemented most of this internal-memory resident code in C, to be linked into a standalone binary embedded in u-boot. This binary is relocated into internal memory by lowlevel_init. After this, most of these functions are calleable from the main DDR resident u-boot through generated stubs that switch stacks and branch to internal memory.
1. Is there a better and/or simpler means to this end?
2. Has the need to run from internal memory in this fashion been faced on any other device that you know of? If so, how was that handled?
3. The monitor code is awkwardly split between SOC specific (mostly) and board specific (e.g. power management IC) pieces. This is currently placed in the appropriate places and pulled together in lib$(BOARD) by mon.mak. Any thoughts if this should be lumped together in one place or restructured in any other way?
4. Any other thoughts/comments/concerns/complaints?
--- MAKEALL | 1 + Makefile | 3 + board/ti/tnetv107xevm/Makefile | 62 +++ board/ti/tnetv107xevm/config.mk | 20 + board/ti/tnetv107xevm/debug.c | 61 +++ board/ti/tnetv107xevm/mon_pmic.c | 267 +++++++++++++ board/ti/tnetv107xevm/pmic.c | 74 ++++ board/ti/tnetv107xevm/sdb_board.c | 168 ++++++++ board/ti/tnetv107xevm/tnetv107x.h | 27 ++ board/ti/tnetv107xevm/u-boot.lds | 52 +++ board/ti/tnetv107xevm/wdt.c | 56 +++ cpu/arm1176/cpu.c | 1 - cpu/arm1176/start.S | 64 +++- cpu/arm1176/tnetv107x/Makefile | 52 +++ cpu/arm1176/tnetv107x/init.c | 34 ++ cpu/arm1176/tnetv107x/mon/README | 61 +++ cpu/arm1176/tnetv107x/mon/lowlevel_init.S | 89 +++++ cpu/arm1176/tnetv107x/mon/mon.lds | 85 ++++ cpu/arm1176/tnetv107x/mon/mon.mak | 70 ++++ cpu/arm1176/tnetv107x/mon/mon_aemif.c | 186 +++++++++ cpu/arm1176/tnetv107x/mon/mon_cache.c | 196 ++++++++++ cpu/arm1176/tnetv107x/mon/mon_clock.c | 578 ++++++++++++++++++++++++++++ cpu/arm1176/tnetv107x/mon/mon_ddr.c | 320 +++++++++++++++ cpu/arm1176/tnetv107x/mon/mon_init.c | 58 +++ cpu/arm1176/tnetv107x/mon/mon_log.c | 183 +++++++++ cpu/arm1176/tnetv107x/mon/mon_mux.c | 465 ++++++++++++++++++++++ cpu/arm1176/tnetv107x/mon/mon_ssp.c | 235 +++++++++++ cpu/arm1176/tnetv107x/mon/mon_stubs.awk | 101 +++++ cpu/arm1176/tnetv107x/mon/mon_timer.c | 167 ++++++++ cpu/arm1176/tnetv107x/mon/mon_wdt.c | 213 ++++++++++ include/asm-arm/arch-tnetv107x/clock.h | 41 ++ include/asm-arm/arch-tnetv107x/emif_defs.h | 28 ++ include/asm-arm/arch-tnetv107x/hardware.h | 300 ++++++++++++++ include/asm-arm/arch-tnetv107x/mux.h | 307 +++++++++++++++ include/asm-arm/arch-tnetv107x/nand_defs.h | 43 ++ include/asm-arm/arch-tnetv107x/ssp.h | 79 ++++ include/configs/smdk6400.h | 6 + include/configs/tnetv107x_evm.h | 361 +++++++++++++++++ 38 files changed, 5103 insertions(+), 11 deletions(-) create mode 100644 board/ti/tnetv107xevm/Makefile create mode 100644 board/ti/tnetv107xevm/config.mk create mode 100644 board/ti/tnetv107xevm/debug.c create mode 100644 board/ti/tnetv107xevm/mon_pmic.c create mode 100644 board/ti/tnetv107xevm/pmic.c create mode 100644 board/ti/tnetv107xevm/sdb_board.c create mode 100644 board/ti/tnetv107xevm/tnetv107x.h create mode 100644 board/ti/tnetv107xevm/u-boot.lds create mode 100644 board/ti/tnetv107xevm/wdt.c create mode 100644 cpu/arm1176/tnetv107x/Makefile create mode 100644 cpu/arm1176/tnetv107x/init.c create mode 100644 cpu/arm1176/tnetv107x/mon/README create mode 100644 cpu/arm1176/tnetv107x/mon/lowlevel_init.S create mode 100644 cpu/arm1176/tnetv107x/mon/mon.lds create mode 100644 cpu/arm1176/tnetv107x/mon/mon.mak create mode 100644 cpu/arm1176/tnetv107x/mon/mon_aemif.c create mode 100644 cpu/arm1176/tnetv107x/mon/mon_cache.c create mode 100644 cpu/arm1176/tnetv107x/mon/mon_clock.c create mode 100644 cpu/arm1176/tnetv107x/mon/mon_ddr.c create mode 100644 cpu/arm1176/tnetv107x/mon/mon_init.c create mode 100644 cpu/arm1176/tnetv107x/mon/mon_log.c create mode 100644 cpu/arm1176/tnetv107x/mon/mon_mux.c create mode 100644 cpu/arm1176/tnetv107x/mon/mon_ssp.c create mode 100644 cpu/arm1176/tnetv107x/mon/mon_stubs.awk create mode 100644 cpu/arm1176/tnetv107x/mon/mon_timer.c create mode 100644 cpu/arm1176/tnetv107x/mon/mon_wdt.c create mode 100644 include/asm-arm/arch-tnetv107x/clock.h create mode 100644 include/asm-arm/arch-tnetv107x/emif_defs.h create mode 100644 include/asm-arm/arch-tnetv107x/hardware.h create mode 100644 include/asm-arm/arch-tnetv107x/mux.h create mode 100644 include/asm-arm/arch-tnetv107x/nand_defs.h create mode 100644 include/asm-arm/arch-tnetv107x/ssp.h create mode 100644 include/configs/tnetv107x_evm.h
diff --git a/MAKEALL b/MAKEALL index 2eb8bb6..7daf414 100755 --- a/MAKEALL +++ b/MAKEALL @@ -624,6 +624,7 @@ LIST_ARM11=" \ mx31pdk_nand \ qong \ smdk6400 \ + tnetv107x_evm \ "
######################################################################### diff --git a/Makefile b/Makefile index 5147df7..3ce4487 100644 --- a/Makefile +++ b/Makefile @@ -2932,6 +2932,9 @@ davinci_dm365evm_config : unconfig davinci_dm6467evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci
+tnetv107x_evm_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm1176 tnetv107xevm ti tnetv107x + imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile new file mode 100644 index 0000000..961ea16 --- /dev/null +++ b/board/ti/tnetv107xevm/Makefile @@ -0,0 +1,62 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +mon = $(SRCTREE)/cpu/$(CPU)/$(SOC)/mon/ + +VPATH = $(src) $(obj) $(mon) + +LIB = $(obj)lib$(BOARD).a + +COBJS += sdb_board.o wdt.o debug.o pmic.o +COBJS_MON += mon_pmic.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +.PHONY: all + +all: $(LIB) + +include $(mon)mon.mak + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/tnetv107xevm/config.mk b/board/ti/tnetv107xevm/config.mk new file mode 100644 index 0000000..f5487cb --- /dev/null +++ b/board/ti/tnetv107xevm/config.mk @@ -0,0 +1,20 @@ +# +# (C) Copyright 2009 +# Cyril Chemparathy, Texas Instruments, cyril@ti.com +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, gj@denx.de +# David Mueller, ELSOFT AG, d.mueller@elsoft.ch +# +# (C) Copyright 2003 +# Texas Instruments, <www.ti.com> +# Swaminathan swami.iyer@ti.com +# +# Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net +# +# (C) Copyright 2008 +# Sekhar Nori, Texas Instruments, Inc. nsekhar@ti.com + +# Provide at least 16MB spacing between us and the Linux Kernel image + +TEXT_BASE = 0x83FC0000 diff --git a/board/ti/tnetv107xevm/debug.c b/board/ti/tnetv107xevm/debug.c new file mode 100644 index 0000000..e0a05c4 --- /dev/null +++ b/board/ti/tnetv107xevm/debug.c @@ -0,0 +1,61 @@ +/* + * SoC-specific debug commands for TNETV107X platforms + * + * (C) Copyright 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> +#include "tnetv107x.h" + +#define SOC_CMD_PMIC "pmic" +#define SOC_CMD_PMIC_USAGE \ + "\t" SOC_CMD_PMIC " read <reg> - read register\n" \ + "\t" SOC_CMD_PMIC " write <reg> <val> - write register\n" \ + "\t" SOC_CMD_PMIC " corevolt [mV] - set core voltage\n" + +#define SOC_CMD_WDT "wdt" +#define SOC_CMD_WDT_USAGE \ + "\t" SOC_CMD_WDT " start <msecs> - start watchdog\n" \ + "\t" SOC_CMD_WDT " stop - stop watchdog\n" \ + "\t" SOC_CMD_WDT " kick - kick watchdog\n" + +int do_soc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int ret = 1; + + if (argc > 1) { + if (strcmp(argv[1], SOC_CMD_PMIC) == 0) + ret = do_pmic(cmdtp, flag, argc - 1, argv + 1); + if (strcmp(argv[1], SOC_CMD_WDT) == 0) + ret = do_wdt(cmdtp, flag, argc - 1, argv + 1); + } + + if (ret) + printf("Usage:\n%s\n", cmdtp->usage); + return ret; +} + +U_BOOT_CMD(soc, 6, 1, do_soc, + "soc - soc debug commands\n", SOC_CMD_PMIC_USAGE SOC_CMD_WDT_USAGE); diff --git a/board/ti/tnetv107xevm/mon_pmic.c b/board/ti/tnetv107xevm/mon_pmic.c new file mode 100644 index 0000000..a043c43 --- /dev/null +++ b/board/ti/tnetv107xevm/mon_pmic.c @@ -0,0 +1,267 @@ +/* + * (C) Copyright 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ssp.h> + +#define PMIC_SSP_PORT 1 +#define PMIC_SSP_CONFIG SSP_EARLY_DIN + +#define PMIC_SSP_IOSEL \ + ( \ + SSP_PIN_SEL(0, SSP_CLOCK) | \ + SSP_PIN_SEL(1, SSP_DATA) | \ + SSP_PIN_SEL(2, SSP_CHIPSEL) | \ + SSP_PIN_SEL(3, SSP_IN) | \ + SSP_INPUT_SEL(3) \ + ) + +#define PMIC_REG_LDO_SET 0x0 +#define PMIC_LDO_ILIM_MASK 1 /* 0 = 400-800, 1 = 900-1500 */ +#define PMIC_LDO_VSEL_MASK 0x0f +#define PMIC_LDO2_ILIM_SHIFT 12 +#define PMIC_LDO2_VSEL_SHIFT 4 +#define PMIC_LDO1_ILIM_SHIFT 8 +#define PMIC_LDO1_VSEL_SHIFT 0 + +#define PMIC_REG_BLOCK_EN 0x1 +#define PMIC_BLOCK_MASK 1 +#define PMIC_BLOCK_LDO1_SHIFT 0 +#define PMIC_BLOCK_LDO2_SHIFT 1 +#define PMIC_BLOCK_LCD_SHIFT 2 +#define PMIC_BLOCK_USB_SHIFT 3 + +#define PMIC_REG_DCDC_SET 0x2 +#define PMIC_DCDC_VDCDC_MASK 0x1f +#define PMIC_DCDC_VDCDC1_SHIFT 0 +#define PMIC_DCDC_VDCDC2_SHIFT 5 +#define PMIC_DCDC_VDCDC3_SHIFT 10 + +#define PMIC_REG_DCDC_EN 0x3 +#define PMIC_DCDCDCDC_EN_MASK 0x1 +#define PMIC_DCDCDCDC1_EN_SHIFT 0 +#define PMIC_DCDCDCDC1_PG_MSK BIT(1) +#define PMIC_DCDCDCDC2_EN_SHIFT 2 +#define PMIC_DCDCDCDC2_PG_MSK BIT(3) +#define PMIC_DCDCDCDC3_EN_SHIFT 4 +#define PMIC_DCDCDCDC3_PG_MSK BIT(5) + +#define PMIC_REG_USB 0x4 +#define PMIC_USB_ILIM_SHIFT 0 +#define PMIC_USB_ILIM_MASK 0x3 +#define PMIC_USB_TSD_SHIFT 2 +#define PMIC_USB_TSD_MASK 0x3 +#define PMIC_USB_TWARN_SHIFT 4 +#define PMIC_USB_TWARN_MASK 0x3 +#define PMIC_USB_IWARN_SD BIT(6) +#define PMIC_USB_FAST_LOOP BIT(7) + +#define PMIC_REG_ALARM 0x5 +#define PMIC_ALARM_LDO1 BIT(0) +#define PMIC_ALARM_DCDC1 BIT(1) +#define PMIC_ALARM_DCDC2 BIT(2) +#define PMIC_ALARM_DCDC3 BIT(3) +#define PMIC_ALARM_LDO2 BIT(4) +#define PMIC_ALARM_USB_WARN BIT(5) +#define PMIC_ALARM_USB_ALARM BIT(6) +#define PMIC_ALARM_LCD BIT(9) +#define PMIC_ALARM_TEMP_WARM BIT(10) +#define PMIC_ALARM_TEMP_HOT BIT(11) +#define PMIC_ALARM_NRST BIT(14) +#define PMIC_ALARM_POWERUP BIT(15) + +#define PMIC_REG_INT_ENABLE 0x6 +#define PMIC_INT_LDO1 BIT(0) +#define PMIC_INT_DCDC1 BIT(1) +#define PMIC_INT_DCDC2 BIT(2) +#define PMIC_INT_DCDC3 BIT(3) +#define PMIC_INT_LDO2 BIT(4) +#define PMIC_INT_USB_WARN BIT(5) +#define PMIC_INT_USB_ALARM BIT(6) +#define PMIC_INT_LCD BIT(9) +#define PMIC_INT_TEMP_WARM BIT(10) +#define PMIC_INT_TEMP_HOT BIT(11) +#define PMIC_INT_GLOBAL_EN BIT(15) + +#define PMIC_REG_INT_STATUS 0x7 +#define PMIC_STATUS_LDO1 BIT(0) +#define PMIC_STATUS_DCDC1 BIT(1) +#define PMIC_STATUS_DCDC2 BIT(2) +#define PMIC_STATUS_DCDC3 BIT(3) +#define PMIC_STATUS_LDO2 BIT(4) +#define PMIC_STATUS_USB_WARN BIT(5) +#define PMIC_STATUS_USB_ALARM BIT(6) +#define PMIC_STATUS_LCD BIT(9) +#define PMIC_STATUS_TEMP_WARM BIT(10) +#define PMIC_STATUS_TEMP_HOT BIT(11) + +#define PMIC_REG_SOFTWARE_RESET 0xb +#define PMIC_REG_WRITE_ENABLE 0xd +#define PMIC_REG_REV_ID 0xf + +#define PMIC_ADDR_MASK 0x03f +#define PMIC_READ 0x000 +#define PMIC_WRITE 0x200 +#define PMIC_ADDR(a, w) (((a)<<10) | w) + + +static u32 pmic_seqmap[] = { +#define PMIC_WRITE_OFFSET 0 + SSP_OPCODE_SHIFT | SSP_OUT_MODE | SSP_ADDR_REG | SSP_COUNT(23), + SSP_OPCODE_SHIFT | SSP_OUT_MODE | SSP_DATA_REG | SSP_COUNT(31), + SSP_OPCODE_SHIFT | SSP_IN_MODE | SSP_ADDR_REG | SSP_COUNT(7), + SSP_OPCODE_STOP | SSP_OUT_MODE | SSP_CS_HIGH, +#define PMIC_WRITE_STOP 3 + +#define PMIC_READ_OFFSET 4 + SSP_OPCODE_SHIFT | SSP_OUT_MODE | SSP_ADDR_REG | SSP_COUNT(23), + SSP_OPCODE_SHIFT | SSP_IN_MODE | SSP_DATA_REG | SSP_COUNT(31), + SSP_OPCODE_SHIFT | SSP_IN_MODE | SSP_ADDR_REG | SSP_COUNT(7), + SSP_OPCODE_STOP | SSP_OUT_MODE | SSP_CS_HIGH, +#define PMIC_READ_STOP 7 +}; + +static int initialized; + +void init_pmic(void) +{ + if (initialized) + return; + + ssp_open(PMIC_SSP_PORT, PMIC_SSP_IOSEL, PMIC_SSP_CONFIG); + + ssp_load(PMIC_SSP_PORT, pmic_seqmap, ARRAY_SIZE(pmic_seqmap)); + + initialized = 1; +} + +void suspend_pmic(void) +{ + if (!initialized) + return; + + ssp_close(PMIC_SSP_PORT); +} + +void restore_pmic(void) +{ + init_pmic(); +} + +int pmic_read(int reg) +{ + int ret; + u32 data; + + init_pmic(); + + data = PMIC_ADDR(reg, PMIC_READ) << 16; + + ret = ssp_run(PMIC_SSP_PORT, PMIC_READ_OFFSET, + data, &data); + + if (ret < 0) + return ret; + + return data & 0xffff; +} + +int pmic_write(int reg, int val) +{ + u32 data; + + init_pmic(); + + data = PMIC_ADDR(reg, PMIC_WRITE) << 16; + data |= (val & 0xffff); + + return ssp_run(PMIC_SSP_PORT, PMIC_WRITE_OFFSET, + data, &data); +} + +int pmic_get_core_voltage(void) +{ + int val; + + val = pmic_read(PMIC_REG_DCDC_SET); + val &= 0x001f; + + return val * 25 + 800; +} + +int pmic_set_core_voltage(int target_voltage) +{ + unsigned long val; + int current_voltage; + int voltage_step; + + if ((target_voltage > 1575) || (target_voltage < 800) + || (target_voltage % 25)) + return -1; + + current_voltage = pmic_get_core_voltage(); + + if (target_voltage == current_voltage) + return 0; /* nothing to do */ + + /* Convert into steps of 25mV */ + current_voltage = (current_voltage - 800) / 25; + target_voltage = (target_voltage - 800) / 25; + + voltage_step = (current_voltage < target_voltage) ? 1 : -1; + + pmic_write(PMIC_REG_WRITE_ENABLE, 1); + + val = pmic_read(PMIC_REG_DCDC_SET); + + wdt_start(2000); /* 2 second hard timeout */ + + do { + current_voltage += voltage_step; + val &= ~0x001f; /* low 5-bits are VCORE_SEL */ + val |= current_voltage; + pmic_write(PMIC_REG_DCDC_SET, val); + udelay(200); /* Allow the step to settle down */ + } while (current_voltage != target_voltage); + + wdt_stop(); + + pmic_write(PMIC_REG_WRITE_ENABLE, 0); + + return 0; +} + +void pmic_usb_set_enable(int enable) +{ + unsigned long val; + + pmic_write(PMIC_REG_WRITE_ENABLE, 1); + + val = pmic_read(PMIC_REG_BLOCK_EN); + val &= ~(1 << 3); + val |= (enable) ? (1 << 3) : 0; + pmic_write(PMIC_REG_BLOCK_EN, val); + + pmic_write(PMIC_REG_WRITE_ENABLE, 0); +} diff --git a/board/ti/tnetv107xevm/pmic.c b/board/ti/tnetv107xevm/pmic.c new file mode 100644 index 0000000..075fd4b --- /dev/null +++ b/board/ti/tnetv107xevm/pmic.c @@ -0,0 +1,74 @@ +/* + * Power-management device support for TNETV107X platforms + * + * (C) Copyright 2009 Texas Instruments Inc. <www.ti.com> + * Author: Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <asm/arch/hardware.h> +#include <asm/arch/clock.h> +#include "tnetv107x.h" + +int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long addr, value; + unsigned long voltage; + + if (argc > 1) { + if (strcmp(argv[1], "read") == 0) { + if (argc != 3) + return 1; + addr = simple_strtoul(argv[2], 0, 0); + value = pmic_read(addr); + printf("read[%lx] - value %lx\n", addr, value); + return 0; + } else if (strcmp(argv[1], "write") == 0) { + if (argc != 4) + return 1; + addr = simple_strtoul(argv[2], 0, 0); + value = simple_strtoul(argv[3], 0, 0); + pmic_write(addr, value); + printf("wrote[%lx] - value %lx\n", addr, value); + return 0; + } else if (strcmp(argv[1], "corevolt") == 0) { + if (argc >= 3) { + voltage = simple_strtoul(argv[2], 0, 10); + if (pmic_set_core_voltage(voltage) < 0) + printf("failed to set core voltage " + "to %ld.%03ld\n", + voltage / 1000, voltage % 1000); + else + printf("successfully set core voltage " + "to %ld.%03ld\n", + voltage / 1000, voltage % 1000); + } else { + voltage = pmic_get_core_voltage(); + printf("current core voltage is %ld.%03ld\n", + voltage / 1000, voltage % 1000); + } + return 0; + } + } + return 1; +} diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c new file mode 100644 index 0000000..a24ea08 --- /dev/null +++ b/board/ti/tnetv107xevm/sdb_board.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2009 Cyril Chemparathy, Texas Instruments, Inc. cyril@ti.com + * + * Modified for TNETV107X SDB. + * + * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. nsekhar@ti.com + * + * Modified for DA8xx EVM. + * + * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include <common.h> +#include <miiphy.h> +#include <linux/mtd/nand.h> +#include <asm/arch/hardware.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/arch/nand_defs.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /*-------------------------------------------------------* + * Mask all IRQs by clearing the global enable and setting + * the enable clear for all the 90 interrupts. This code is + * also included in low level init. Including it here in case + * low level init is skipped. Not removing it from low level + * init in case some of the low level init code generates + * interrupts... Not expected... but you never know... + *-------------------------------------------------------*/ + +#ifndef CONFIG_USE_IRQ + __raw_writel(0, INTC_GLB_EN); /* Global disable */ + __raw_writel(0, INTC_HINT_EN); /* Disable host ints */ + __raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */ + __raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */ + __raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */ +#endif + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_TNETV107X; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + clk_enable(TNETV107X_LPSC_WDT_ARM); + +#if defined(CONFIG_DRIVER_TI_CPSW3G) + eth_hw_init(0x55555555, 0xaaaaaaaa); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#define PHY_PAGE 22 +#define PHY_MSCR 21 +#define PHY_CSCR 16 +#define PHY_PAGE_MSCR 2 +#define PHY_PAGE_DEFAULT 0 + +#if defined(CONFIG_DRIVER_TI_CPSW3G) +void board_init_phy(int instance, int id) +{ + unsigned short reg; + + /* Program RXID and TXID */ + if (miiphy_write("cpsw3g", id, PHY_PAGE, PHY_PAGE_MSCR) != 0) { + printf("failed to select mscr page\n"); + return; + } + + if (miiphy_read("cpsw3g", id, PHY_MSCR, ®) != 0) { + printf("failed to read mscr\n"); + return; + } + + reg |= 0x3 << 4; /* RXID and TXID */ + + if (miiphy_write("cpsw3g", id, PHY_MSCR, reg) != 0) { + printf("failed to write mscr\n"); + return; + } + + /* Program AutoCross */ + if (miiphy_write("cpsw3g", id, PHY_PAGE, PHY_PAGE_DEFAULT) != 0) { + printf("failed to select cscr page\n"); + return; + } + + reg = 0x0060; + if (miiphy_write("cpsw3g", id, PHY_CSCR, reg) != 0) { + printf("failed to write cscr\n"); + return; + } + + /* Enable Autonegotiation */ + if (miiphy_read("cpsw3g", id, PHY_BMCR, ®) != 0) { + printf("failed to read bmcr\n"); + return; + } + + reg |= PHY_BMCR_AUTON; + + if (miiphy_write("cpsw3g", id, PHY_BMCR, reg) != 0) { + printf("failed to write bmcr\n"); + return; + } + + /* Setup Advertisement */ + if (miiphy_read("cpsw3g", id, PHY_ANAR, ®) != 0) { + printf("failed to read anar\n"); + return; + } + + reg |= (0x1f << 5); + + if (miiphy_write("cpsw3g", id, PHY_ANAR, reg) != 0) { + printf("failed to write anar\n"); + return; + } + + /* PHY Soft Reset */ + if (miiphy_reset("cpsw3g", id) != 0) + printf("failed to soft-reset phy\n"); +} +#endif + +#ifdef CONFIG_NAND_DAVINCI +int board_nand_init(struct nand_chip *nand) +{ + davinci_nand_init(nand); + + return 0; +} +#endif diff --git a/board/ti/tnetv107xevm/tnetv107x.h b/board/ti/tnetv107xevm/tnetv107x.h new file mode 100644 index 0000000..faf6cee --- /dev/null +++ b/board/ti/tnetv107xevm/tnetv107x.h @@ -0,0 +1,27 @@ +/* + * SoC-specific include for TNETV107X and similar chips + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __TNETV107X_CPU_H__ +#define __TNETV107X_CPU_H__ + +int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int do_wdt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +#endif /* __TNETV107X_CPU_H__ */ diff --git a/board/ti/tnetv107xevm/u-boot.lds b/board/ti/tnetv107xevm/u-boot.lds new file mode 100644 index 0000000..785df6d --- /dev/null +++ b/board/ti/tnetv107xevm/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm1176/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +} diff --git a/board/ti/tnetv107xevm/wdt.c b/board/ti/tnetv107xevm/wdt.c new file mode 100644 index 0000000..7e1ee2e --- /dev/null +++ b/board/ti/tnetv107xevm/wdt.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <config.h> +#include <command.h> +#include <asm/arch/hardware.h> +#include <asm/arch/clock.h> +#include "tnetv107x.h" + +int do_wdt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long msec; + int ret; + + if (argc > 1) { + if (strcmp(argv[1], "start") == 0) { + if (argc != 3) + return 1; + msec = simple_strtoul(argv[2], 0, 0); + ret = wdt_start(msec); + printf("Watchdog start for expiry at %ld msecs - %s\n", + msec, ret ? "FAIL" : "OK"); + return ret; + } else if (strcmp(argv[1], "stop") == 0) { + ret = wdt_stop(); + printf("Watchdog stop - %s\n", ret ? "FAIL" : "OK"); + return ret; + } else if (strcmp(argv[1], "kick") == 0) { + ret = wdt_kick(); + printf("Watchdog kick - %s\n", ret ? "FAIL" : "OK"); + return ret; + } + } + return 1; +} diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index 2c0014f..c0fd114 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -33,7 +33,6 @@
#include <common.h> #include <command.h> -#include <asm/arch/s3c6400.h> #include <asm/system.h>
static void cache_flush (void); diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S index 68a356d..beec574 100644 --- a/cpu/arm1176/start.S +++ b/cpu/arm1176/start.S @@ -1,5 +1,5 @@ /* - * armboot - Startup Code for S3C6400/ARM1176 CPU-core + * armboot - Startup Code for ARM1176 CPU-core * * Copyright (c) 2007 Samsung Electronics * @@ -35,7 +35,6 @@ #ifdef CONFIG_ENABLE_MMU #include <asm/proc/domain.h> #endif -#include <asm/arch/s3c6400.h>
#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE @@ -145,6 +144,7 @@ reset: * ************************************************************************* */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* * we do sys-critical inits only at reboot, * not when booting from ram! @@ -170,6 +170,8 @@ cpu_init_crit: bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) orr r0, r0, #0x00000002 @ set bit 2 (A) Align orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + +#ifdef CONFIG_ENABLE_MMU /* Prepare to disable the MMU */ adr r1, mmu_disable_phys /* We presume we're within the first 1024 bytes */ @@ -187,20 +189,60 @@ mmu_disable: nop nop mov pc, r2 -#endif - mmu_disable_phys: +#else + mcr p15, 0, r0, c1, c0, 0 +#endif + +#ifdef CONFIG_DISABLE_TCM + /* + * Disable the TCMs + */ + mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ + cmp r0, #0 + beq skip_tcmdisable + mov r1, #0 + mov r2, #1 + tst r0, r2 + mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ + tst r0, r2, LSL #16 + mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ +skip_tcmdisable: +#endif +#endif + +#ifdef CONFIG_PERIPORT_REMAP /* Peri port setup */ - ldr r0, =0x70000000 - orr r0, r0, #0x13 + ldr r0, =CONFIG_PERIPORT_BASE + orr r0, r0, #CONFIG_PERIPORT_SIZE mcr p15,0,r0,c15,c2,4 @ 256M (0x70000000 - 0x7fffffff) +#endif
/* * Go setup Memory and board specific bits prior to relocation. */ bl lowlevel_init /* go setup pll,mux,memory */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-after_copy: #ifdef CONFIG_ENABLE_MMU enable_mmu: /* enable domain access */ @@ -236,9 +278,9 @@ mmu_enable: nop nop mov pc, r2 -#endif - skip_hw_init: +#endif + /* Set up the stack */ stack_setup: ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */ @@ -306,6 +348,8 @@ phy_last_jump: mov r0, #0 mov pc, r9 #endif + + /* ************************************************************************* * @@ -373,7 +417,7 @@ phy_last_jump: ldr r13, _armboot_start /* move past malloc pool */ sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) - /* move to reserved a couple spots for abort stack */ + /* reserved a couple spots for abort stack */ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
/* save caller lr in position 0 of saved stack */ diff --git a/cpu/arm1176/tnetv107x/Makefile b/cpu/arm1176/tnetv107x/Makefile new file mode 100644 index 0000000..6235d63 --- /dev/null +++ b/cpu/arm1176/tnetv107x/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2009 +# Texas Instruments Inc., <www.ti.com> +# Cyril Chemparathy cyril@ti.com +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y += init.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm1176/tnetv107x/init.c b/cpu/arm1176/tnetv107x/init.c new file mode 100644 index 0000000..dbe0b5f --- /dev/null +++ b/cpu/arm1176/tnetv107x/init.c @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <config.h> + +int timer_init(void) +{ + /* + * Nothing here, timer should already have been initialized during + * early_init() in the monitor code + */ + return 0; +} diff --git a/cpu/arm1176/tnetv107x/mon/README b/cpu/arm1176/tnetv107x/mon/README new file mode 100644 index 0000000..be26a39 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/README @@ -0,0 +1,61 @@ +# (C) Copyright 2009 +# Texas Instruments Inc., <www.ti.com> +# Cyril Chemparathy cyril@ti.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + + +The TNETV107X SoC specific code has a small portion of itself (a monitor of +some sort) resident in internal memory (@0x20000000). The following is roughly +what the convoluted build process looks like: + + mux.o clock.o init.o + | | | + +--------+--------+ + | + libtnetv107x_mon.a platform libs + | | + +------------------+---------------+ + | + mon.elf + | + +------------------+--------------------+ + | | + mon.bin (flat binary) mon_stubs.[Sh] (wrapper stubs) + | | + mon.o (bin embedded in elf) mon_stubs.o + | | + +--------------------+------------------+ + | + linked with u-boot + +The monitor code is then copied into internal memory by lowlevel_init.S. +After this, monitor routines are calleable from u-boot through the stub +implementations. The stubs are responsible for switching stacks so as +to run internal-memory resident code entirely from an internal-memory +resident stack. + +By these means, the monitor is entirely independent of external devices, +and can therefore happily muck around with PLLs and EMIFs without substantial +issues even after system initialization. + +Note that the monitor code is by no means intended to be reentrant, since +there is only one stack. However, at some future point of time, this code may +be used as the seed for a resident secure kernel simpler than the TrustZone +stack. diff --git a/cpu/arm1176/tnetv107x/mon/lowlevel_init.S b/cpu/arm1176/tnetv107x/mon/lowlevel_init.S new file mode 100644 index 0000000..1966b55 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/lowlevel_init.S @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/hardware.h> +#include "mon_stubs.h" + +/* + * This code needs to carefully restore lr, ip registers on return + * Registers used/clobbered: r0-r6 + */ +.globl lowlevel_init +lowlevel_init: + mov r5, lr + mov r6, ip + ldr r0, =mon_bss_begin_value + ldr r1, =mon_bss_end_value + mov r2, #0x00000000 +clearbss: + cmp r0, r1 + bge clearbss_done + str r2, [r0] + add r0, r0, #4 + b clearbss +clearbss_done: + + + ldr r0, =mon_stack_begin_value + ldr r1, =mon_stack_end_value + ldr r2, =0xdeadbeef +fillstack: + cmp r0, r1 + bge fillstack_done + str r2, [r0] + add r0, r0, #4 + b fillstack +fillstack_done: + + /* determine load offset */ +current: + adr r0, current + ldr r1, =current + sub r4, r1, r0 + + ldr r0, =MON_START_SYM + sub r0, r0, r4 + ldr r1, =MON_END_SYM + sub r1, r1, r4 + ldr r2, =mon_text_begin_value + + /* relocate monitor code to internal memory */ +reloc: + cmp r0, r1 + bge reloc_done + ldrb r3, [r0] + strb r3, [r2] + add r0, r0, #1 + add r2, r2, #1 + b reloc +reloc_done: + + /* Now finally get around to actually initializing stuff */ + mov r0, r4 + bl early_init + + mov ip, r6 + mov lr, r5 + mov pc, lr diff --git a/cpu/arm1176/tnetv107x/mon/mon.lds b/cpu/arm1176/tnetv107x/mon/mon.lds new file mode 100644 index 0000000..3315836 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon.lds @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SECTIONS +{ + . = 0x20000000; + + . = ALIGN(4); + _scratch_begin = .; + .scratch : { + . = . + 0x1000; + } = 0xdeadbeef + _scratch_end = .; + + _log_begin = .; + .log : { + . = . + 0x1000; + } = 0xdeadbeef + _log_end = .; + + . = ALIGN(4); + _stack_begin = .; + .stack : { + . = . + 0x1000; + } = 0xdeadbeef + _stack_end = .; + + . = ALIGN(4); + _bss_begin = .; + .bss : { + *(.bss) + } = 0x00000000 + _bss_end = .; + + . = ALIGN(4); + _text_begin = .; + .text : + { + *(.text) + *(.text.*) + } + _text_end = .; + + . = ALIGN(4); + _rodata_begin = .; + .rodata : { + *(.rodata) + } + _rodata_end = .; + + . = ALIGN(4); + _data_begin = .; + .data : { + *(.data) + } + _data_end = .; + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); +} diff --git a/cpu/arm1176/tnetv107x/mon/mon.mak b/cpu/arm1176/tnetv107x/mon/mon.mak new file mode 100644 index 0000000..b637c47 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon.mak @@ -0,0 +1,70 @@ +# +# (C) Copyright 2009 +# Texas Instruments Inc., <www.ti.com> +# Cyril Chemparathy cyril@ti.com +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Figure out the start and end symbols generated by LD when the monitor +# executable is embedded into an ELF object. This simply substitutes all +# non-alpha-numeric characters with an underscore. +# +# See mangle_name() in BFD binary.c +# +sanitized := $(shell echo -n $(obj)mon.bin | tr -C '[:alnum:]' '[_*]') +AFLAGS_lowlevel_init.o += -DMON_START_SYM=_binary_$(sanitized)_start +AFLAGS_lowlevel_init.o += -DMON_END_SYM=_binary_$(sanitized)_end +AFLAGS_lowlevel_init.o += $(foreach path,$(VPATH) .,-I$(path)) + +LIB_MON = $(obj)lib$(SOC)_mon.a + +OBJS += $(obj)mon.o +SOBJS += $(obj)lowlevel_init.o $(obj)mon_stubs.o + +COBJS_MON += mon_clock.o mon_mux.o mon_init.o +COBJS_MON += mon_wdt.o mon_timer.o mon_ddr.o +COBJS_MON += mon_aemif.o mon_cache.o mon_log.o +COBJS_MON += mon_ssp.o +OBJS_MON := $(addprefix $(obj),$(COBJS_MON)) + +$(obj)lowlevel_init.o: $(obj)mon_stubs.h + +$(obj)mon.elf: $(LIB_MON) $(mon)mon.lds Makefile + $(LD) -Bstatic -T $(mon)mon.lds -whole-archive $(LIB_MON) \ + --no-whole-archive $(PLATFORM_LIBS) -o $@ + +$(obj)mon.bin: $(obj)mon.elf Makefile + $(OBJCOPY) --gap-fill=0x00 -O binary $< $@ + +$(obj)mon.o: $(obj)mon.bin Makefile + $(LD) -r -b binary -o $@ $< + +$(obj)mon_stubs.S $(obj)mon_stubs.h: $(obj)mon.elf Makefile $(mon)mon_stubs.awk + $(NM) --defined-only $< | awk -f $(mon)mon_stubs.awk -v \ + header=$(obj)mon_stubs.h -v source=$(obj)mon_stubs.S + +$(LIB_MON): $(OBJS_MON) + $(AR) $(ARFLAGS) $@ $(OBJS_MON) diff --git a/cpu/arm1176/tnetv107x/mon/mon_aemif.c b/cpu/arm1176/tnetv107x/mon/mon_aemif.c new file mode 100644 index 0000000..ca5db3c --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_aemif.c @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/mux.h> + +#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE +#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4) +#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c) +#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60) +#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4) + +#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) +#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) +#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26) +#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20) +#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17) +#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13) +#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7) +#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4) +#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2) +#define CONFIG_WIDTH(v) (((v) & 0x03) << 0) + +#define NUM_CS 4 +#define MASK 0xffffffff + +static struct async_emif_config default_async_emif_config[NUM_CS] = { + { /* CS0 */ + .mode = ASYNC_EMIF_MODE_NAND, + .select_strobe = ASYNC_EMIF_CS0_SELECT_STROBE, + .extend_wait = ASYNC_EMIF_CS0_EXTEND_WAIT, + .wr_setup = ASYNC_EMIF_CS0_WR_SETUP, + .wr_strobe = ASYNC_EMIF_CS0_WR_STROBE, + .wr_hold = ASYNC_EMIF_CS0_WR_HOLD, + .rd_setup = ASYNC_EMIF_CS0_RD_SETUP, + .rd_strobe = ASYNC_EMIF_CS0_RD_STROBE, + .rd_hold = ASYNC_EMIF_CS0_RD_HOLD, + .turn_around = ASYNC_EMIF_CS0_TURN_AROUND, + .width = ASYNC_EMIF_CS0_WIDTH, + }, + { /* CS1 */ + .mode = ASYNC_EMIF_MODE_NOR, + .select_strobe = ASYNC_EMIF_CS1_SELECT_STROBE, + .extend_wait = ASYNC_EMIF_CS1_EXTEND_WAIT, + .wr_setup = ASYNC_EMIF_CS1_WR_SETUP, + .wr_strobe = ASYNC_EMIF_CS1_WR_STROBE, + .wr_hold = ASYNC_EMIF_CS1_WR_HOLD, + .rd_setup = ASYNC_EMIF_CS1_RD_SETUP, + .rd_strobe = ASYNC_EMIF_CS1_RD_STROBE, + .rd_hold = ASYNC_EMIF_CS1_RD_HOLD, + .turn_around = ASYNC_EMIF_CS1_TURN_AROUND, + .width = ASYNC_EMIF_CS1_WIDTH, + }, + { /* CS2 */ + .mode = ASYNC_EMIF_MODE_NOR, + .select_strobe = ASYNC_EMIF_CS2_SELECT_STROBE, + .extend_wait = ASYNC_EMIF_CS2_EXTEND_WAIT, + .wr_setup = ASYNC_EMIF_CS2_WR_SETUP, + .wr_strobe = ASYNC_EMIF_CS2_WR_STROBE, + .wr_hold = ASYNC_EMIF_CS2_WR_HOLD, + .rd_setup = ASYNC_EMIF_CS2_RD_SETUP, + .rd_strobe = ASYNC_EMIF_CS2_RD_STROBE, + .rd_hold = ASYNC_EMIF_CS2_RD_HOLD, + .turn_around = ASYNC_EMIF_CS2_TURN_AROUND, + .width = ASYNC_EMIF_CS2_WIDTH, + }, + { /* CS3 */ + .mode = ASYNC_EMIF_MODE_NOR, + .select_strobe = ASYNC_EMIF_CS3_SELECT_STROBE, + .extend_wait = ASYNC_EMIF_CS3_EXTEND_WAIT, + .wr_setup = ASYNC_EMIF_CS3_WR_SETUP, + .wr_strobe = ASYNC_EMIF_CS3_WR_STROBE, + .wr_hold = ASYNC_EMIF_CS3_WR_HOLD, + .rd_setup = ASYNC_EMIF_CS3_RD_SETUP, + .rd_strobe = ASYNC_EMIF_CS3_RD_STROBE, + .rd_hold = ASYNC_EMIF_CS3_RD_HOLD, + .turn_around = ASYNC_EMIF_CS3_TURN_AROUND, + .width = ASYNC_EMIF_CS3_WIDTH, + }, +}; + +void configure_async_emif(int cs, struct async_emif_config *cfg) +{ + unsigned long tmp; + + if (cfg->mode == ASYNC_EMIF_MODE_NAND) { + tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL); + tmp |= (1 << cs); + __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL); + + } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) { + tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL); + tmp |= (1 << cs); + __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL); + } + + tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs)); + + if (cfg->select_strobe != -1) { + tmp &= ~CONFIG_SELECT_STROBE(MASK); + tmp |= CONFIG_SELECT_STROBE(cfg->select_strobe); + } + if (cfg->extend_wait != -1) { + tmp &= ~CONFIG_EXTEND_WAIT(MASK); + tmp |= CONFIG_EXTEND_WAIT(cfg->extend_wait); + } + if (cfg->wr_setup != -1) { + tmp &= ~CONFIG_WR_SETUP(MASK); + tmp |= CONFIG_WR_SETUP(cfg->wr_setup); + } + if (cfg->wr_strobe != -1) { + tmp &= ~CONFIG_WR_STROBE(MASK); + tmp |= CONFIG_WR_STROBE(cfg->wr_strobe); + } + if (cfg->wr_hold != -1) { + tmp &= ~CONFIG_WR_HOLD(MASK); + tmp |= CONFIG_WR_HOLD(cfg->wr_hold); + } + if (cfg->rd_setup != -1) { + tmp &= ~CONFIG_RD_SETUP(MASK); + tmp |= CONFIG_RD_SETUP(cfg->rd_setup); + } + if (cfg->rd_strobe != -1) { + tmp &= ~CONFIG_RD_STROBE(MASK); + tmp |= CONFIG_RD_STROBE(cfg->rd_strobe); + } + if (cfg->rd_hold != -1) { + tmp &= ~CONFIG_RD_HOLD(MASK); + tmp |= CONFIG_RD_HOLD(cfg->rd_hold); + } + if (cfg->turn_around != -1) { + tmp &= ~CONFIG_TURN_AROUND(MASK); + tmp |= CONFIG_TURN_AROUND(cfg->turn_around); + } + if (cfg->width != -1) { + tmp &= ~CONFIG_WIDTH(MASK); + tmp |= CONFIG_WIDTH(cfg->width); + } + + __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs)); +} + +void init_async_emif(void) +{ + int cs; + + mux_select_pin(TNETV107X_PIN_ASR_CS3); + + lpsc_control(TNETV107X_LPSC_AEMIF, PSC_MDCTL_NEXT_ENABLE); + + for (cs = 0; cs < NUM_CS; cs++) + configure_async_emif(cs, &default_async_emif_config[cs]); +} + +void suspend_async_emif(void) +{ + /* do nothing */ +} + +void resume_async_emif(void) +{ + /* do nothing */ +} diff --git a/cpu/arm1176/tnetv107x/mon/mon_cache.c b/cpu/arm1176/tnetv107x/mon/mon_cache.c new file mode 100644 index 0000000..0f2b028 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_cache.c @@ -0,0 +1,196 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, Inc. <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* + * CPU specific code + */ + +#define C1_MMU (1<<0) +#define C1_ALIGN (1<<1) +#define C1_DC (1<<2) +#define C1_WB (1<<3) +#define C1_BIG_ENDIAN (1<<7) +#define C1_SYS_PROT (1<<8) +#define C1_ROM_PROT (1<<9) +#define C1_IC (1<<12) +#define C1_HIGH_VECTORS (1<<13) +#define RESERVED_1 (0xf << 3) + +#define DCACHE_LINE 32 +#define DCACHE_MASK (DCACHE_LINE - 1) + +#define cp15_read(crn, crm, op1, op2) \ +({ \ + unsigned long __res; \ + __asm__ __volatile__ ( \ + "mrc p15, " #op1 ", %0, " #crn ", " #crm ", " #op2 "\n" \ + : "=r" (__res) : : "memory"); \ + (__res); \ +}) + +#define cp15_write(crn, crm, op1, op2, value) \ +do { \ + unsigned long __res = (value); \ + __asm__ __volatile__ ( \ + "mcr p15, " #op1 ", %0, " #crn ", " #crm ", " #op2 "\n" \ + : : "r" (__res) : "memory"); \ +} while (0) + +#define cp15_c1_read() cp15_read(c1, c0, 0, 0) +#define cp15_c1_write(v) cp15_write(c1, c0, 0, 0, v) + +void icache_enable(void) +{ + ulong reg; + + reg = cp15_c1_read(); /* get control reg. */ + clk_delay(); + cp15_c1_write(reg | C1_IC); +} + +void icache_disable(void) +{ + ulong reg; + + reg = cp15_c1_read(); + clk_delay(); + cp15_c1_write(reg & ~C1_IC); +} + +int icache_status(void) +{ + return (cp15_c1_read() & C1_IC) != 0; +} + +void dcache_enable(void) +{ + ulong reg; + + reg = cp15_c1_read(); /* get control reg. */ + clk_delay(); + cp15_c1_write(reg | C1_DC); +} + +void dcache_disable(void) +{ + ulong reg; + + reg = cp15_c1_read(); + clk_delay(); + cp15_c1_write(reg & ~C1_DC); +} + +int dcache_status(void) +{ + return (cp15_c1_read() & C1_DC) != 0; +} + +void icache_invalidate(void) +{ + /** + * The following code is the suggested work-around for ARM1176 core + * errata #415045 (Invalidate Entire Instruction Cache operation + * might fail to invalidate some lines if coincident with linefill). + * + * See release 12.0 or * later of the errata document for more + * information. + */ + asm volatile ("mov r0, #0 \n" + "mrs r1, cpsr \n" + /* Invalidate Entire Instruction Cache */ + "mcr p15, 0, r0, c7, c5, 0 \n" + /* Invalidate Entire Instruction Cache */ + "mcr p15, 0, r0, c7, c5, 0 \n" + /* Invalidate Entire Instruction Cache */ + "mcr p15, 0, r0, c7, c5, 0 \n" + /* Invalidate Entire Instruction Cache */ + "mcr p15, 0, r0, c7, c5, 0 \n" + /* Reenable interrupts */ + "msr cpsr_c, r1 \n" + "nop \n" + "nop \n" + "nop \n" + "nop \n" + "nop \n" + "nop \n" + "nop \n" + "nop \n" + "nop \n" + "nop \n" + "nop \n" + /* Flush Prefetch Buffer */ + "mcr p15, 0, r0, c7, c5, 4 \n" + /* Flush BTAC */ + "mcr p15, 0, r0, c7, c5, 6 \n"); +} + +void dcache_range_invalidate(void *addr, unsigned long size) +{ + unsigned long start = (unsigned long)addr; + unsigned long end = start + size; + + if (start & DCACHE_MASK) { + start &= ~DCACHE_MASK; + cp15_write(c7, c10, 0, 1, start); + } + + if (end & DCACHE_MASK) { + end &= ~DCACHE_MASK; + cp15_write(c7, c14, 0, 1, end); + } + + for (; start < end; start += DCACHE_LINE) + cp15_write(c7, c6, 0, 1, start); + + cp15_write(c7, c10, 0, 4, 0); +} + +void dcache_range_clean(void *addr, unsigned long size) +{ + unsigned long start = (unsigned long)addr; + unsigned long end = start + size; + + for (start &= ~DCACHE_MASK; start < end; start += DCACHE_LINE) + cp15_write(c7, c10, 0, 1, start); + cp15_write(c7, c10, 0, 4, 0); +} + +void dcache_range_flush(void *addr, unsigned long size) +{ + unsigned long start = (unsigned long)addr; + unsigned long end = start + size; + + for (start &= ~DCACHE_MASK; start < end; start += DCACHE_LINE) + cp15_write(c7, c14, 0, 1, start); + cp15_write(c7, c10, 0, 4, 0); +} diff --git a/cpu/arm1176/tnetv107x/mon/mon_clock.c b/cpu/arm1176/tnetv107x/mon/mon_clock.c new file mode 100644 index 0000000..9bae305 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_clock.c @@ -0,0 +1,578 @@ +/* + * Copyright (C) 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> + +#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE +#define PSC_BASE TNETV107X_PSC_BASE + +#define MAX_PREDIV 64 +#define MAX_POSTDIV 8 +#define MAX_MULT 512 +#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV) + +/* LPSC registers */ +#define PSC_PTCMD 0x120 +#define PSC_PTSTAT 0x128 +#define PSC_MDSTAT(n) (0x800 + (n) * 4) +#define PSC_MDCTL(n) (0xA00 + (n) * 4) + +#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg))) +#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg))) + +/* PLL identifiers */ +enum pll_type_e { + SYS_PLL, + TDM_PLL, + ETH_PLL +}; + +/* PLL configuration data */ +struct pll_init_data { + int config_enable; + int pll; + int internal_osc; + unsigned long external_freq; + unsigned long pll_freq; + unsigned long div_freq[10]; +}; + +/* SSPLL registers */ +struct sspll_regs { + u32 modes; + u32 post_div; + u32 pre_div; + u32 mult_factor; + u32 divider_range; + u32 bw_divider; + u32 spr_amount; + u32 spr_rate_div; + u32 diag; +}; + +/* SSPLL base addresses */ +static struct sspll_regs *sspll_regs[] = { + (struct sspll_regs *)(CLOCK_BASE + 0x040), + (struct sspll_regs *)(CLOCK_BASE + 0x080), + (struct sspll_regs *)(CLOCK_BASE + 0x0c0), +}; + +#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg)) +#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg)) +#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg)) + + +/* PLL Control Registers */ +struct pllctl_regs { + u32 ctl; /* 00 */ + u32 ocsel; /* 04 */ + u32 secctl; /* 08 */ + u32 __pad0; + u32 mult; /* 10 */ + u32 prediv; /* 14 */ + u32 div1; /* 18 */ + u32 div2; /* 1c */ + u32 div3; /* 20 */ + u32 oscdiv1; /* 24 */ + u32 postdiv; /* 28 */ + u32 bpdiv; /* 2c */ + u32 wakeup; /* 30 */ + u32 __pad1; + u32 cmd; /* 38 */ + u32 stat; /* 3c */ + u32 alnctl; /* 40 */ + u32 dchange; /* 44 */ + u32 cken; /* 48 */ + u32 ckstat; /* 4c */ + u32 systat; /* 50 */ + u32 ckctl; /* 54 */ + u32 __pad2[2]; + u32 div4; /* 60 */ + u32 div5; /* 64 */ + u32 div6; /* 68 */ + u32 div7; /* 6c */ + u32 div8; /* 70 */ +}; + +static struct pllctl_regs *pllctl_regs[] = { + (struct pllctl_regs *)(CLOCK_BASE + 0x700), + (struct pllctl_regs *)(CLOCK_BASE + 0x300), + (struct pllctl_regs *)(CLOCK_BASE + 0x500), +}; + +#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) +#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) +#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) + +/* PLLCTL Bits */ +#define PLLCTL_CLKMODE (0x1 << 8) +#define PLLCTL_PLLSELB (0x1 << 7) +#define PLLCTL_PLLENSRC (0x1 << 5) +#define PLLCTL_PLLDIS (0x1 << 4) +#define PLLCTL_PLLRST (0x1 << 3) +#define PLLCTL_PLLPWRDN (0x1 << 1) +#define PLLCTL_PLLEN (0x1 << 0) + +static int pll_div_offset[] = { + offsetof(struct pllctl_regs, div1), + offsetof(struct pllctl_regs, div2), + offsetof(struct pllctl_regs, div3), + offsetof(struct pllctl_regs, div4), + offsetof(struct pllctl_regs, div5), + offsetof(struct pllctl_regs, div6), + offsetof(struct pllctl_regs, div7), + offsetof(struct pllctl_regs, div8), +}; + +static unsigned long pll_bypass_mask[] = { 1, 4, 2 }; +static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff }; + +/* Mappings from PLL+DIV to subsystem clocks */ +#define priv(pll, div) ((pll) | (div << 4)) +#define priv_to_pll(priv) ((priv) & 0x0f) +#define priv_to_div(priv) ((priv) >> 4) + +#define sys_arm1176_clk priv(SYS_PLL, 0) +#define sys_dsp_clk priv(SYS_PLL, 1) +#define sys_ddr_clk priv(SYS_PLL, 2) +#define sys_full_clk priv(SYS_PLL, 3) +#define sys_lcd_clk priv(SYS_PLL, 4) +#define sys_vlynq_ref_clk priv(SYS_PLL, 5) +#define sys_tsc_clk priv(SYS_PLL, 6) +#define sys_half_clk priv(SYS_PLL, 7) + +#define eth_clk_5 priv(ETH_PLL, 0) +#define eth_clk_50 priv(ETH_PLL, 1) +#define eth_clk_125 priv(ETH_PLL, 2) +#define eth_clk_250 priv(ETH_PLL, 3) +#define eth_clk_25 priv(ETH_PLL, 4) + +#define tdm_clk priv(TDM_PLL, 0) +#define tdm_extra_clk priv(TDM_PLL, 1) +#define tdm1_clk priv(TDM_PLL, 2) + +static const unsigned lpsc_clk_map[] = { + [TNETV107X_LPSC_ARM] = sys_arm1176_clk, + [TNETV107X_LPSC_GEM] = sys_dsp_clk, + [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk, + [TNETV107X_LPSC_TPCC] = sys_full_clk, + [TNETV107X_LPSC_TPTC0] = sys_full_clk, + [TNETV107X_LPSC_TPTC1] = sys_full_clk, + [TNETV107X_LPSC_RAM] = sys_full_clk, + [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk, + [TNETV107X_LPSC_LCD] = sys_lcd_clk, + [TNETV107X_LPSC_ETHSS] = eth_clk_125, + [TNETV107X_LPSC_AEMIF] = sys_full_clk, + [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk, + [TNETV107X_LPSC_TSC] = sys_tsc_clk, + [TNETV107X_LPSC_ROM] = sys_half_clk, + [TNETV107X_LPSC_UART2] = sys_half_clk, + [TNETV107X_LPSC_PKTSEC] = sys_half_clk, + [TNETV107X_LPSC_SECCTL] = sys_half_clk, + [TNETV107X_LPSC_KEYMGR] = sys_half_clk, + [TNETV107X_LPSC_KEYPAD] = sys_half_clk, + [TNETV107X_LPSC_GPIO] = sys_half_clk, + [TNETV107X_LPSC_MDIO] = sys_half_clk, + [TNETV107X_LPSC_SDIO0] = sys_half_clk, + [TNETV107X_LPSC_UART0] = sys_half_clk, + [TNETV107X_LPSC_UART1] = sys_half_clk, + [TNETV107X_LPSC_TIMER0] = sys_half_clk, + [TNETV107X_LPSC_TIMER1] = sys_half_clk, + [TNETV107X_LPSC_WDT_ARM] = sys_half_clk, + [TNETV107X_LPSC_WDT_DSP] = sys_half_clk, + [TNETV107X_LPSC_SSP] = sys_half_clk, + [TNETV107X_LPSC_TDM0] = tdm_clk, + [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk, + [TNETV107X_LPSC_MCDMA] = sys_half_clk, + [TNETV107X_LPSC_USB0] = sys_half_clk, + [TNETV107X_LPSC_TDM1] = tdm1_clk, + [TNETV107X_LPSC_DEBUGSS] = sys_half_clk, + [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250, + [TNETV107X_LPSC_SYSTEM] = sys_half_clk, + [TNETV107X_LPSC_IMCOP] = sys_dsp_clk, + [TNETV107X_LPSC_SPARE] = sys_half_clk, + [TNETV107X_LPSC_SDIO1] = sys_half_clk, + [TNETV107X_LPSC_USB1] = sys_half_clk, + [TNETV107X_LPSC_USBSS] = sys_half_clk, + [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk, + [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk, +}; + +static const struct pll_init_data plls[] = { + [SYS_PLL] = { + .config_enable = 1, + .pll = SYS_PLL, + .internal_osc = CONFIG_PLL_SYS_INT_OSC, + .external_freq = CONFIG_PLL_SYS_EXT_FREQ, + .pll_freq = CONFIG_PLL_SYS_PLL_FREQ, + .div_freq = { + CONFIG_PLL_SYS_ARM1176_CLK, + CONFIG_PLL_SYS_DSP_CLK, + CONFIG_PLL_SYS_DDR_CLK, + CONFIG_PLL_SYS_FULL_CLK, + CONFIG_PLL_SYS_LCD_CLK, + CONFIG_PLL_SYS_VLYNQ_REF_CLK, + CONFIG_PLL_SYS_TSC_CLK, + CONFIG_PLL_SYS_HALF_CLK, + }, + }, + [TDM_PLL] = { + .config_enable = CONFIG_PLL_TDM_CONFIG, + .pll = TDM_PLL, + .internal_osc = CONFIG_PLL_TDM_INT_OSC, + .external_freq = CONFIG_PLL_TDM_EXT_FREQ, + .pll_freq = CONFIG_PLL_TDM_PLL_FREQ, + .div_freq = { + CONFIG_PLL_TDM_TDM0_CLK, + CONFIG_PLL_TDM_TIMER_CLK, + CONFIG_PLL_TDM_TDM1_CLK, + }, + }, + [ETH_PLL] = { + .config_enable = CONFIG_PLL_ETH_CONFIG, + .pll = ETH_PLL, + .internal_osc = CONFIG_PLL_ETH_INT_OSC, + .external_freq = CONFIG_PLL_ETH_EXT_FREQ, + .pll_freq = CONFIG_PLL_ETH_PLL_FREQ, + .div_freq = { + CONFIG_PLL_ETH_5_CLK, + CONFIG_PLL_ETH_50_CLK, + CONFIG_PLL_ETH_125_CLK, + CONFIG_PLL_ETH_250_CLK, + CONFIG_PLL_ETH_25_CLK, + }, + }, +}; + +void clk_delay(void) +{ + int i; + + for (i = 0; i < 1000; i++) { + /* Optimization barrier to keep GCC from mucking around */ + __asm__ __volatile__("mov r0, r0\n" : : : "memory"); + } +} + +static unsigned long pll_freq_get(int pll) +{ + unsigned long mult = 1, prediv = 1, postdiv = 1; + unsigned long ref = CONFIG_SYS_INT_OSC_FREQ; + unsigned long ret; + u32 bypass; + + bypass = __raw_readl((u32 *)(CLOCK_BASE)); + if (!(bypass & pll_bypass_mask[pll])) { + mult = sspll_reg_read(pll, mult_factor); + prediv = sspll_reg_read(pll, pre_div) + 1; + postdiv = sspll_reg_read(pll, post_div) + 1; + } + + if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE) + ref = plls[pll].external_freq; + + if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN)) + return ref; + + ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256); + ret /= (prediv * postdiv); + + return ret; +} + +static unsigned long __pll_div_freq_get(int pll, unsigned int fpll, + int div) +{ + int divider = 1; + unsigned long divreg; + + divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]); + + if (divreg & (0x01 << 15)) + divider = (divreg & pll_div_mask[pll]) + 1; + + return fpll / divider; +} + +static unsigned long pll_div_freq_get(int pll, int div) +{ + unsigned int fpll = pll_freq_get(pll); + + return __pll_div_freq_get(pll, fpll, div); +} + +static void __pll_div_freq_set(int pll, unsigned int fpll, int div, + unsigned long hz) +{ + int divider = (fpll / hz - 1); + + divider &= pll_div_mask[pll]; + divider |= (0x01 << 15); /* enable */ + + __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]); + pllctl_reg_write(pll, alnctl, + pllctl_reg_read(pll, alnctl) | (1 << div)); + pllctl_reg_write(pll, dchange, + pllctl_reg_read(pll, dchange) | (1 << div)); +} + +static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz) +{ + unsigned int fpll = pll_freq_get(pll); + + __pll_div_freq_set(pll, fpll, div, hz); + + /* GO */ + pllctl_reg_write(pll, cmd, 1); + + /* Wait for completion */ + while (pllctl_reg_read(pll, stat) & 0x01) + ; + + clk_delay(); + + return __pll_div_freq_get(pll, fpll, div); +} + +unsigned long clk_get_rate(unsigned int clk) +{ + int div, pll; + + pll = priv_to_pll(lpsc_clk_map[clk]); + div = priv_to_div(lpsc_clk_map[clk]); + + return pll_div_freq_get(pll, div); +} + +long clk_round_rate(unsigned int clk, unsigned long hz) +{ + int div, fpll, divider, pll; + + pll = priv_to_pll(lpsc_clk_map[clk]); + div = priv_to_div(lpsc_clk_map[clk]); + fpll = pll_freq_get(pll); + divider = (fpll / hz - 1); + divider &= pll_div_mask[pll]; + + return fpll / (divider + 1); +} + +int clk_set_rate(unsigned int clk, unsigned long _hz) +{ + unsigned long hz; + int div, pll; + + hz = clk_round_rate(clk, _hz); + if (hz != _hz) + return -1; /* Cannot set to target freq */ + + pll = priv_to_pll(lpsc_clk_map[clk]); + div = priv_to_div(lpsc_clk_map[clk]); + + return pll_div_freq_set(pll, div, hz); +} + +int clk_get(unsigned int id) +{ + return clk_get_rate(id); +} + +static void __lpsc_set_state(int nmod, int lrstz, va_list args) +{ + int i; + u32 mdctl, state; + unsigned int id; + + for (i = 0; i < nmod; i++) { + id = va_arg(args, unsigned int); + state = va_arg(args, u32); + mdctl = psc_reg_read(PSC_MDCTL(id)); + mdctl &= ~0x1f; + mdctl |= state; + if (lrstz == 0 || lrstz == 1) { + mdctl &= ~(1 << 8); + mdctl |= (lrstz << 8); + } + psc_reg_write(PSC_MDCTL(id), mdctl); + } +} + +static void __lpsc_wait_state(int nmod, va_list args) +{ + int i; + u32 state; + unsigned int id; + + for (i = 0; i < nmod; i++) { + id = va_arg(args, unsigned int); + state = va_arg(args, u32); + while ((psc_reg_read(PSC_MDSTAT(id)) & 0x1f) != state) + ; + } +} + +void __lpsc_control(int nmod, int lrstz, ...) +{ + va_list args; + + va_start(args, lrstz); + __lpsc_set_state(nmod, lrstz, args); + va_end(args); + + psc_reg_write(PSC_PTCMD, 1); + while (psc_reg_read(PSC_PTSTAT) & 1) + ; + + va_start(args, lrstz); + __lpsc_wait_state(nmod, args); + va_end(args); +} + +void lpsc_control(unsigned int id, u32 state) +{ + __lpsc_control(1, -1, id, state); +} + +int lpsc_status(unsigned int id) +{ + return psc_reg_read(PSC_MDSTAT(id)) & 0x1f; +} + +void clk_enable(unsigned int id) +{ + lpsc_control(id, PSC_MDCTL_NEXT_ENABLE); +} + +void clk_disable(unsigned int id) +{ + lpsc_control(id, PSC_MDCTL_NEXT_DISABLE); +} + +static void init_pll(const struct pll_init_data *data) +{ + unsigned long fpll; + unsigned long best_prediv = 0, best_postdiv = 0, best_mult = 0; + unsigned long div, prediv, postdiv, mult; + unsigned long delta, actual; + long best_delta = -1; + int i; + u32 tmp; + + if (!data->config_enable) + return; + + tmp = pllctl_reg_read(data->pll, ctl); + if (data->internal_osc) { + tmp &= ~PLLCTL_CLKMODE; + fpll = CONFIG_SYS_INT_OSC_FREQ; + } else { + tmp |= PLLCTL_CLKMODE; + fpll = data->external_freq; + } + pllctl_reg_write(data->pll, ctl, tmp); + + mult = data->pll_freq / fpll; + for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) { + div = (fpll * mult) / data->pll_freq; + if (div < 1 || div > MAX_DIV) + continue; + + for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) { + prediv = div / postdiv; + if (prediv < 1 || prediv > MAX_PREDIV) + continue; + + actual = (fpll / prediv) * (mult / postdiv); + delta = (actual - data->pll_freq); + delta = ABS(delta); + if ((delta < best_delta) || (best_delta == -1)) { + best_delta = delta; + best_mult = mult; + best_prediv = prediv; + best_postdiv = postdiv; + if (delta == 0) + goto done; + } + } + } +done: + + fpll = fpll * best_mult; + fpll /= best_prediv * best_postdiv; + + pllctl_reg_write(data->pll, ctl, + pllctl_reg_read(data->pll, ctl) & + ~PLLCTL_PLLENSRC); + pllctl_reg_write(data->pll, ctl, + pllctl_reg_read(data->pll, ctl) & + ~PLLCTL_PLLEN); + clk_delay(); + + pllctl_reg_write(data->pll, ctl, + pllctl_reg_read(data->pll, ctl) | + PLLCTL_PLLRST); + clk_delay(); + + pllctl_reg_write(data->pll, ctl, + pllctl_reg_read(data->pll, ctl) & + ~PLLCTL_PLLPWRDN); + pllctl_reg_write(data->pll, ctl, + pllctl_reg_read(data->pll, ctl) & + ~PLLCTL_PLLDIS); + clk_delay(); + + sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8); + sspll_reg_write(data->pll, pre_div, best_prediv - 1); + sspll_reg_write(data->pll, post_div, best_postdiv - 1); + + for (i = 0; i < 10; i++) + if (data->div_freq[i]) + __pll_div_freq_set(data->pll, fpll, i, + data->div_freq[i]); + + /* GO */ + pllctl_reg_write(data->pll, cmd, 1); + + /* Wait for completion */ + while (pllctl_reg_read(data->pll, stat) & 0x01) + ; + + clk_delay(); + + pllctl_reg_write(data->pll, ctl, + pllctl_reg_read(data->pll, ctl) & + ~PLLCTL_PLLRST); + clk_delay(); + pllctl_reg_write(data->pll, ctl, + pllctl_reg_read(data->pll, ctl) | + PLLCTL_PLLEN); + clk_delay(); +} + +void init_plls(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(plls); i++) + init_pll(&plls[i]); +} diff --git a/cpu/arm1176/tnetv107x/mon/mon_ddr.c b/cpu/arm1176/tnetv107x/mon/mon_ddr.c new file mode 100644 index 0000000..c3f1e62 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_ddr.c @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> + +/* DDR EMIF Registers */ +#define EMIFCTL_BASE TNETV107X_DDR_EMIF_CONTROL_BASE +#define EMIFCTL_DRAMCTL (EMIFCTL_BASE+0x08) +#define EMIFCTL_REFRESH (EMIFCTL_BASE+0x0c) +#define EMIFCTL_TIMING_1 (EMIFCTL_BASE+0x10) +#define EMIFCTL_TIMING_2 (EMIFCTL_BASE+0x14) +#define EMIFCTL_PHYCTL (EMIFCTL_BASE+0xe4) +#define EMIFCTL_PR_OLD_COUNT (EMIFCTL_BASE+0x20) + +#define DRAMCTL_BOOT_UNLOCK (1 << 23) +#define DRAMCTL_TIMING_UNLOCK (1 << 15) + +#define DRAMCTL_MSDRAM_ENABLE (1 << 25) +#define DRAMCTL_DDR2_ENABLE (1 << 20) +#define DRAMCTL_DDR_ENABLE (1 << 17) +#define DRAMCTL_SDRAM_ENABLE (1 << 16) + +#define DRAMCTL_DDR2_TERM(v) ((((v) & 1) << 21) | (((v) & 2) << 26)) +#define DRAMCTL_IBANK_POS(v) ((v) ? 1 << 26 : 0) +#define DRAMCTL_DRIVE(v) ((((v) & 1) << 18) | (((v) & 2) << 23)) +#define DRAMCTL_DDR2_DDQS(v) ((v) ? 1 << 22 : 0) + +#define DRAMCTL_NARROW_MODE(v) ((v) ? 1 << 14 : 0) +#define DRAMCTL_CL(v) (((v) & 0x7) << 9) +#define DRAMCTL_IBANK(v) (((v) & 0x7) << 4) +#define DRAMCTL_EBANK(v) ((v) ? 1 << 3 : 0) +#define DRAMCTL_PAGE_SIZE(v) (((v) & 0x7) << 0) + +#define REFRESH_LP_MODE (1 << 31) +#define REFRESH_SR_PD (1 << 23) + +#define MASK 0xffffffff + +static struct ddr_emif_config default_emif_config = { + .type = DDR_EMIF_TYPE, + .ddr2_term = DDR_EMIF_TERM, + .drive = DDR_EMIF_DRIVE, + .ddr2_ddqs = DDR_EMIF_DDQS, + .ibank_pos = DDR_EMIF_IBANK_POS, + .narrow_mode = DDR_EMIF_NARROW_MODE, + .ibank = DDR_EMIF_IBANK, + .ebank = DDR_EMIF_EBANK, + .page_size = DDR_EMIF_PAGE_SIZE, + .t_rfc = DDR_EMIF_T_RFC, + .t_rp = DDR_EMIF_T_RP, + .t_rcd = DDR_EMIF_T_RCD, + .t_wr = DDR_EMIF_T_WR, + .t_ras = DDR_EMIF_T_RAS, + .t_rc = DDR_EMIF_T_RC, + .t_rrd = DDR_EMIF_T_RRD, + .t_xsnr = DDR_EMIF_T_XSNR, + .t_rtp = DDR_EMIF_T_RTP, + .t_ras_max = DDR_EMIF_T_RAS_MAX, + .refresh_int = DDR_EMIF_REFRESH_INT, + .t_xsrd = DDR_EMIF_T_XSRD, + .t_xp = DDR_EMIF_T_XP, + .t_aond = DDR_EMIF_T_AOND, + .t_wtr = DDR_EMIF_T_WTR, + .t_cke = DDR_EMIF_T_CKE, + .cas_latency = DDR_EMIF_CAS_LATENCY, + .read_latency = DDR_EMIF_READ_LATENCY, + .pr_old_count = DDR_EMIF_PR_OLD_COUNT, +}; + +static unsigned long ddr_mode_bits[] = { + [SDRAM_TYPE_DDR2] = DRAMCTL_DDR2_ENABLE | + DRAMCTL_DDR_ENABLE | DRAMCTL_SDRAM_ENABLE, + + [SDRAM_TYPE_DDR] = DRAMCTL_DDR_ENABLE | DRAMCTL_SDRAM_ENABLE, + + [SDRAM_TYPE_SDR] = DRAMCTL_SDRAM_ENABLE, + + [SDRAM_TYPE_MOBILE_SDR] = DRAMCTL_MSDRAM_ENABLE | DRAMCTL_SDRAM_ENABLE, + + [SDRAM_TYPE_MOBILE_DDR] = DRAMCTL_MSDRAM_ENABLE | + DRAMCTL_DDR_ENABLE | DRAMCTL_SDRAM_ENABLE, +}; + +static inline int ddr_cas_latency(struct ddr_emif_config *cfg) +{ + int cl = cfg->cas_latency; + + switch (cfg->type) { + case SDRAM_TYPE_SDR: + case SDRAM_TYPE_MOBILE_SDR: + cl /= 10; + if (cl < 2 || cl > 3) + cl = 3; + break; + + case SDRAM_TYPE_DDR: + case SDRAM_TYPE_MOBILE_DDR: + if (cl >= 20 && cl <= 30) + cl /= 10; + else if (cl <= 15) + cl = 5; + else + cl = 6; + break; + + case SDRAM_TYPE_DDR2: + cl /= 10; + if (cl < 2 || cl > 5) + cl = 5; + break; + default: + cl = 3; + } + return cl; +} + +void __configure_ddr(struct ddr_emif_config *cfg, unsigned long ddrclk) +{ + unsigned long ddrtick; + unsigned long tmp; + unsigned long refresh, timing1, timing2; + + ddrclk /= (2 * 1000 * 1000); /* 1/100 ns */ + + timing1 = timing2 = 0; + + refresh = (cfg->refresh_int * ddrclk) / 1000; + ddrtick = (100 * 1000) / ddrclk; /* 1/100 ns */ + + tmp = DIV_CEILING(cfg->t_rfc, ddrtick) << 25; + timing1 |= tmp; + + tmp = DIV_CEILING(cfg->t_rp, ddrtick) << 22; + timing1 |= tmp; + + tmp = DIV_CEILING(cfg->t_rcd, ddrtick) << 19; + timing1 |= tmp; + + tmp = DIV_CEILING(cfg->t_wr, ddrtick) << 16; + timing1 |= tmp; + + tmp = DIV_CEILING(cfg->t_ras, ddrtick) << 11; + timing1 |= tmp; + + tmp = DIV_CEILING(cfg->t_rc, ddrtick) << 6; + timing1 |= tmp; + + tmp = DIV_CEILING(cfg->t_rrd, ddrtick) << 3; + timing1 |= tmp; + + tmp = (cfg->t_wtr - 1) << 0; + timing1 |= tmp; + + tmp = DIV_FLOOR(cfg->t_ras_max, cfg->refresh_int) << 27; + timing2 |= tmp; + + if (cfg->type == SDRAM_TYPE_DDR2) { + tmp = (MAX(cfg->t_xp, cfg->t_cke) - 1) << 25; + timing2 |= tmp; + + tmp = (cfg->cas_latency / 10 - cfg->t_aond - 1) << 23; + timing2 |= tmp; + + tmp = DIV_CEILING(cfg->t_rtp, ddrtick) << 5; + timing2 |= tmp; + + tmp = (cfg->t_cke - 1) << 0; + timing2 |= tmp; + } else { + tmp = DIV_CEILING(cfg->t_ras, ddrtick) << 0; + timing2 |= tmp; + } + + tmp = DIV_CEILING(cfg->t_xsnr, ddrtick) << 16; + timing2 |= tmp; + + tmp = (cfg->t_xsrd - 1) << 8; + timing2 |= tmp; + + tmp = __raw_readl(EMIFCTL_DRAMCTL); + __raw_writel(tmp | DRAMCTL_BOOT_UNLOCK, EMIFCTL_DRAMCTL); + + tmp &= + ~(DRAMCTL_MSDRAM_ENABLE | DRAMCTL_DDR_ENABLE | DRAMCTL_DDR2_ENABLE | + DRAMCTL_SDRAM_ENABLE | DRAMCTL_BOOT_UNLOCK); + tmp |= ddr_mode_bits[cfg->type]; + + tmp &= ~DRAMCTL_DDR2_TERM(MASK); + tmp |= DRAMCTL_DDR2_TERM(cfg->ddr2_term); + + tmp &= ~DRAMCTL_DRIVE(MASK); + tmp |= DRAMCTL_DRIVE(cfg->drive); + + tmp &= ~DRAMCTL_DDR2_DDQS(MASK); + tmp |= DRAMCTL_DDR2_DDQS(cfg->ddr2_ddqs); + + tmp &= ~DRAMCTL_IBANK_POS(MASK); + tmp |= DRAMCTL_IBANK_POS(cfg->ibank_pos); + + __raw_writel(tmp, EMIFCTL_DRAMCTL); + tmp = __raw_readl(EMIFCTL_DRAMCTL); + + __raw_writel(tmp | DRAMCTL_TIMING_UNLOCK, EMIFCTL_DRAMCTL); + tmp = __raw_readl(EMIFCTL_DRAMCTL); + + __raw_writel(timing1, EMIFCTL_TIMING_1); + __raw_writel(timing2, EMIFCTL_TIMING_2); + + tmp &= ~DRAMCTL_CL(MASK); + tmp |= DRAMCTL_CL(ddr_cas_latency(cfg)); + + tmp &= ~DRAMCTL_IBANK(MASK); + tmp |= DRAMCTL_IBANK(cfg->ibank); + + tmp &= ~DRAMCTL_EBANK(MASK); + tmp |= DRAMCTL_EBANK(cfg->ebank); + + tmp &= ~DRAMCTL_NARROW_MODE(MASK); + tmp |= DRAMCTL_NARROW_MODE(cfg->narrow_mode); + + tmp &= ~DRAMCTL_PAGE_SIZE(MASK); + tmp |= DRAMCTL_PAGE_SIZE(cfg->page_size); + + __raw_writel(tmp, EMIFCTL_DRAMCTL); + __raw_writel(__raw_readl(EMIFCTL_DRAMCTL) & ~DRAMCTL_TIMING_UNLOCK, + EMIFCTL_DRAMCTL); + + __raw_writel((__raw_readl(EMIFCTL_PHYCTL) & ~0x7) | + cfg->read_latency, EMIFCTL_PHYCTL);; + + __raw_writel(refresh, EMIFCTL_REFRESH); + __raw_writel(cfg->pr_old_count, EMIFCTL_PR_OLD_COUNT); +} + +void configure_ddr(struct ddr_emif_config *cfg) +{ + __configure_ddr(cfg, clk_get_rate(TNETV107X_LPSC_DDR2_PHY)); +} + +void init_ddr_emif(void) +{ + if (lpsc_status(TNETV107X_LPSC_DDR2_PHY) < PSC_MDCTL_NEXT_ENABLE) { + /* DDR not initialized by BootROM */ + __lpsc_control(1, 1, TNETV107X_LPSC_DDR2_PHY, + PSC_MDCTL_NEXT_ENABLE); + clk_delay(); + __lpsc_control(2, 1, TNETV107X_LPSC_DDR2_EMIF1_VRST, + PSC_MDCTL_NEXT_ENABLE, + TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST, + PSC_MDCTL_NEXT_ENABLE); + clk_delay(); + } + + configure_ddr(&default_emif_config); + + lpsc_control(TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST, + PSC_MDCTL_NEXT_DISABLE); + lpsc_control(TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST, + PSC_MDCTL_NEXT_SWRSTDISABLE); + lpsc_control(TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST, + PSC_MDCTL_NEXT_DISABLE); + lpsc_control(TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST, + PSC_MDCTL_NEXT_SYNCRST); + lpsc_control(TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST, PSC_MDCTL_NEXT_ENABLE); +} + +void suspend_ddr_emif(void) +{ + unsigned long tmp; + + if (lpsc_status(TNETV107X_LPSC_DDR2_PHY) < PSC_MDCTL_NEXT_ENABLE) + return; + + tmp = __raw_readl(EMIFCTL_REFRESH); + tmp |= REFRESH_LP_MODE; + tmp &= ~REFRESH_SR_PD; + __raw_writel(tmp, EMIFCTL_REFRESH); + for (tmp = 0; tmp < 1000; tmp++) + clk_delay(); +} + +void restore_ddr_emif(void) +{ + unsigned long tmp; + + if (lpsc_status(TNETV107X_LPSC_DDR2_PHY) < PSC_MDCTL_NEXT_ENABLE) { + init_ddr_emif(); + return; + } + + tmp = __raw_readl(EMIFCTL_REFRESH); + tmp &= ~REFRESH_LP_MODE; + __raw_writel(tmp, EMIFCTL_REFRESH); + + for (tmp = 0; tmp < 1000; tmp++) + clk_delay(); +} diff --git a/cpu/arm1176/tnetv107x/mon/mon_init.c b/cpu/arm1176/tnetv107x/mon/mon_init.c new file mode 100644 index 0000000..e8e5ac8 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_init.c @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> + +void chip_configuration_unlock(void) +{ + __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0); + __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1); +} + +void early_init(unsigned long load_offset) +{ + init_log(); + icache_invalidate(); + icache_enable(); + chip_configuration_unlock(); + suspend_ddr_emif(); + init_plls(); + init_ddr_emif(); + init_timer(); + init_async_emif(); + init_ssp(); + init_pmic(); + init_wdt(); +} + +void lowlevel_shutdown(void) +{ + suspend_wdt(); + suspend_pmic(); + suspend_ssp(); + suspend_timer(); +} diff --git a/cpu/arm1176/tnetv107x/mon/mon_log.c b/cpu/arm1176/tnetv107x/mon/mon_log.c new file mode 100644 index 0000000..87643df --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_log.c @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Simple logging module that saves printf()'d content into an internal memory + * buffer. Invaluable in early monitor debugging. See the linker script + * mon.lds to determine the location of this buffer. + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> + +static unsigned char *log_ptr; + +static inline int log_full(void) +{ + return log_ptr >= ((&_log_end) - 1); +} + +void log_char(unsigned char c) +{ + if (!log_full()) + *log_ptr++ = c; + *log_ptr = '\0'; +} + +void log_str(const char *str) +{ + while (!log_full() && *str) + log_char(*str++); +} + +void log_number(unsigned long num, int base, int sign) +{ + int digit; + const char *digits = "0123456789abcdef"; + + if (sign && ((long)num < 0)) { + log_char('-'); + num = -num; + } + if (!num) + log_char('0'); + else if (num < base) + log_char(digits[num]); + else { + digit = num % base; + num = num / base; + log_number(num, base, 0); + log_char(digits[digit]); + } +} + +void init_log(void) +{ + log_clear(); +} + +void log_clear(void) +{ + log_ptr = &_log_begin; + while (!log_full()) + log_char('\0'); + log_ptr = &_log_begin; +} + +void __vprintf(const char *fmt, va_list args) +{ + unsigned long num; + int base, sign; + const char *s; + int qualifier; + + for (; *fmt; ++fmt) { + if (*fmt != '%') { + log_char(*fmt); + continue; + } + + ++fmt; + + /* get the conversion qualifier */ + qualifier = -1; + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'q') { + qualifier = *fmt; + if (qualifier == 'l' && *(fmt + 1) == 'l') { + qualifier = 'q'; + ++fmt; + } + ++fmt; + } + + /* default base */ + base = 10; + sign = 0; + + switch (*fmt) { + case 'c': + log_char((unsigned char)va_arg(args, int)); + continue; + + case 's': + s = va_arg(args, char *); + if (!s) + s = "<NULL>"; + log_str(s); + continue; + + case 'p': + log_number((unsigned long)va_arg(args, void *), 16, 0); + continue; + + case '%': + log_char('%'); + continue; + + case 'o': + base = 8; + break; + + case 'X': + case 'x': + base = 16; + break; + + case 'd': + case 'i': + sign = 1; + case 'u': + break; + + default: + log_char('%'); + if (*fmt) + log_char(*fmt); + else + --fmt; + continue; + } + + if (qualifier == 'l') + num = va_arg(args, unsigned long); + else if (qualifier == 'h') { + num = (unsigned short)va_arg(args, int); + if (sign) + num = (short)num; + } else if (sign) + num = va_arg(args, int); + else + num = va_arg(args, unsigned int); + log_number(num, base, sign); + } +} + +void printf(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + __vprintf(fmt, args); + va_end(args); +} diff --git a/cpu/arm1176/tnetv107x/mon/mon_mux.c b/cpu/arm1176/tnetv107x/mon/mon_mux.c new file mode 100644 index 0000000..6e3182d --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_mux.c @@ -0,0 +1,465 @@ +/* + * Copyright (C) 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * Shamelessly cloned from kernel, arch/arm/mach-tnetv107x/mux_cfg.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/mux.h> + +#define MUX_MODE_1 0x00 +#define MUX_MODE_2 0x04 +#define MUX_MODE_3 0x0c +#define MUX_MODE_4 0x1c + +#define MUX_DEBUG 0 + +static const struct pin_config pin_table[] = { + TNETV107X_MUX_CFG(0, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(0, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(0, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(0, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(0, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(0, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(0, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(0, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(0, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(0, 20, MUX_MODE_2), + TNETV107X_MUX_CFG(0, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(0, 25, MUX_MODE_2), + TNETV107X_MUX_CFG(1, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(1, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(1, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(1, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(1, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(1, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(1, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(1, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(1, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(1, 20, MUX_MODE_2), + TNETV107X_MUX_CFG(1, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(1, 25, MUX_MODE_2), + TNETV107X_MUX_CFG(2, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(2, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(2, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(2, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(2, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(2, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(2, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(2, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(2, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(2, 20, MUX_MODE_2), + TNETV107X_MUX_CFG(2, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(2, 25, MUX_MODE_2), + TNETV107X_MUX_CFG(3, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(3, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(3, 0, MUX_MODE_4), + TNETV107X_MUX_CFG(3, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(3, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(3, 5, MUX_MODE_4), + TNETV107X_MUX_CFG(3, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(3, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(3, 10, MUX_MODE_4), + TNETV107X_MUX_CFG(3, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(3, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(3, 15, MUX_MODE_4), + TNETV107X_MUX_CFG(3, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(3, 20, MUX_MODE_2), + TNETV107X_MUX_CFG(3, 20, MUX_MODE_4), + TNETV107X_MUX_CFG(3, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(3, 25, MUX_MODE_2), + TNETV107X_MUX_CFG(3, 25, MUX_MODE_4), + TNETV107X_MUX_CFG(4, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(4, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(4, 0, MUX_MODE_4), + TNETV107X_MUX_CFG(4, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(4, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(4, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(4, 15, MUX_MODE_4), + TNETV107X_MUX_CFG(4, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(4, 20, MUX_MODE_3), + TNETV107X_MUX_CFG(4, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(4, 25, MUX_MODE_4), + TNETV107X_MUX_CFG(5, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(5, 0, MUX_MODE_4), + TNETV107X_MUX_CFG(5, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(5, 5, MUX_MODE_4), + TNETV107X_MUX_CFG(5, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(5, 10, MUX_MODE_4), + TNETV107X_MUX_CFG(5, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(5, 15, MUX_MODE_4), + TNETV107X_MUX_CFG(5, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(5, 20, MUX_MODE_4), + TNETV107X_MUX_CFG(5, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(5, 25, MUX_MODE_4), + TNETV107X_MUX_CFG(6, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(6, 0, MUX_MODE_4), + TNETV107X_MUX_CFG(6, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(6, 5, MUX_MODE_4), + TNETV107X_MUX_CFG(6, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(6, 10, MUX_MODE_4), + TNETV107X_MUX_CFG(6, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(6, 15, MUX_MODE_4), + TNETV107X_MUX_CFG(6, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(6, 20, MUX_MODE_4), + TNETV107X_MUX_CFG(6, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(6, 25, MUX_MODE_4), + TNETV107X_MUX_CFG(7, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(7, 0, MUX_MODE_4), + TNETV107X_MUX_CFG(7, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(7, 5, MUX_MODE_4), + TNETV107X_MUX_CFG(7, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(7, 10, MUX_MODE_4), + TNETV107X_MUX_CFG(7, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(7, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(7, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(7, 20, MUX_MODE_2), + TNETV107X_MUX_CFG(7, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(7, 25, MUX_MODE_2), + TNETV107X_MUX_CFG(8, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(8, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(8, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(8, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(8, 5, MUX_MODE_4), + TNETV107X_MUX_CFG(8, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(8, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(9, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(9, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(9, 0, MUX_MODE_4), + TNETV107X_MUX_CFG(9, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(9, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(9, 5, MUX_MODE_4), + TNETV107X_MUX_CFG(9, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(9, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(9, 10, MUX_MODE_4), + TNETV107X_MUX_CFG(9, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(9, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(9, 15, MUX_MODE_4), + TNETV107X_MUX_CFG(9, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(9, 20, MUX_MODE_2), + TNETV107X_MUX_CFG(9, 20, MUX_MODE_4), + TNETV107X_MUX_CFG(10, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(10, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(10, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(10, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(10, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(10, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(10, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(10, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(10, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(10, 20, MUX_MODE_2), + TNETV107X_MUX_CFG(10, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(10, 25, MUX_MODE_2), + TNETV107X_MUX_CFG(11, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(11, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(12, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(12, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(12, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(12, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(12, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(12, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(13, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(13, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(13, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(13, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(14, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(14, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(14, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(14, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(14, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(14, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(15, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(15, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(15, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(15, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(15, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(15, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(15, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(15, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(16, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(16, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(16, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(16, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(16, 10, MUX_MODE_3), + TNETV107X_MUX_CFG(16, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(16, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(17, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(17, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(17, 0, MUX_MODE_3), + TNETV107X_MUX_CFG(17, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(17, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(17, 5, MUX_MODE_3), + TNETV107X_MUX_CFG(17, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(17, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(17, 10, MUX_MODE_3), + TNETV107X_MUX_CFG(17, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(17, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(17, 15, MUX_MODE_3), + TNETV107X_MUX_CFG(18, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(18, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(18, 0, MUX_MODE_3), + TNETV107X_MUX_CFG(18, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(18, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(18, 5, MUX_MODE_3), + TNETV107X_MUX_CFG(18, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(18, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(18, 10, MUX_MODE_3), + TNETV107X_MUX_CFG(18, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(18, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(18, 15, MUX_MODE_3), + TNETV107X_MUX_CFG(19, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(19, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(19, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(19, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(19, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(19, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(20, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(20, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(20, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(20, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(20, 15, MUX_MODE_3), + TNETV107X_MUX_CFG(20, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(20, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(21, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(21, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(21, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(21, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(21, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(21, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(22, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(22, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(22, 5, MUX_MODE_3), + TNETV107X_MUX_CFG(22, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(22, 10, MUX_MODE_3), + TNETV107X_MUX_CFG(22, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(22, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(22, 15, MUX_MODE_3), + TNETV107X_MUX_CFG(22, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(22, 20, MUX_MODE_3), + TNETV107X_MUX_CFG(22, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(22, 25, MUX_MODE_3), + TNETV107X_MUX_CFG(23, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(23, 0, MUX_MODE_3), + TNETV107X_MUX_CFG(23, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(23, 5, MUX_MODE_3), + TNETV107X_MUX_CFG(23, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(23, 10, MUX_MODE_3), + TNETV107X_MUX_CFG(24, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(24, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(24, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(24, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(24, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(24, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(24, 10, MUX_MODE_3), + TNETV107X_MUX_CFG(24, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(24, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(24, 15, MUX_MODE_3), + TNETV107X_MUX_CFG(24, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(24, 20, MUX_MODE_2), + TNETV107X_MUX_CFG(24, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(24, 25, MUX_MODE_2), + TNETV107X_MUX_CFG(25, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(25, 0, MUX_MODE_2), + TNETV107X_MUX_CFG(25, 0, MUX_MODE_3), + TNETV107X_MUX_CFG(25, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(25, 5, MUX_MODE_2), + TNETV107X_MUX_CFG(25, 5, MUX_MODE_3), + TNETV107X_MUX_CFG(25, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(25, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(25, 10, MUX_MODE_3), + TNETV107X_MUX_CFG(25, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(25, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(25, 15, MUX_MODE_3), + TNETV107X_MUX_CFG(25, 15, MUX_MODE_4), + TNETV107X_MUX_CFG(26, 0, MUX_MODE_1), + TNETV107X_MUX_CFG(26, 5, MUX_MODE_1), + TNETV107X_MUX_CFG(26, 10, MUX_MODE_1), + TNETV107X_MUX_CFG(26, 10, MUX_MODE_2), + TNETV107X_MUX_CFG(26, 15, MUX_MODE_1), + TNETV107X_MUX_CFG(26, 15, MUX_MODE_2), + TNETV107X_MUX_CFG(26, 20, MUX_MODE_1), + TNETV107X_MUX_CFG(26, 20, MUX_MODE_2), + TNETV107X_MUX_CFG(26, 25, MUX_MODE_1), + TNETV107X_MUX_CFG(26, 25, MUX_MODE_2), +}; + +const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]); + +static const short sdio0_pins[] = { + TNETV107X_PIN_SDIO0_CLK, TNETV107X_PIN_SDIO0_CMD, + TNETV107X_PIN_SDIO0_DATA0, + TNETV107X_PIN_SDIO0_DATA1, TNETV107X_PIN_SDIO0_DATA2, + TNETV107X_PIN_SDIO0_DATA3, + -1 +}; + +static const short sdio1_pins[] = { + TNETV107X_PIN_SDIO1_CLK_0, TNETV107X_PIN_SDIO1_CMD_0, + TNETV107X_PIN_SDIO1_DATA0_0, TNETV107X_PIN_SDIO1_DATA1_0, + TNETV107X_PIN_SDIO1_DATA2_0, TNETV107X_PIN_SDIO1_DATA3_0, + -1 +}; + +static const short uart0_pins[] = { + TNETV107X_PIN_UART0_CTS, TNETV107X_PIN_UART0_RD, + TNETV107X_PIN_UART0_RTS, + TNETV107X_PIN_UART0_TD, -1 +}; + +static const short uart1_pins[] = { + TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1 +}; + +static const short uart2_pins[] = { + TNETV107X_PIN_UART2_CTS, TNETV107X_PIN_UART2_RD, + TNETV107X_PIN_UART2_RTS, + TNETV107X_PIN_UART2_TD, -1 +}; + +static const short keypad_pins[] = { + TNETV107X_PIN_KEYPAD_R0, TNETV107X_PIN_KEYPAD_R1, + TNETV107X_PIN_KEYPAD_R2, + TNETV107X_PIN_KEYPAD_R3, TNETV107X_PIN_KEYPAD_R4, + TNETV107X_PIN_KEYPAD_R5, + TNETV107X_PIN_KEYPAD_R6, TNETV107X_PIN_KEYPAD_C0, + TNETV107X_PIN_KEYPAD_C1, + TNETV107X_PIN_KEYPAD_C2, TNETV107X_PIN_KEYPAD_C3, + TNETV107X_PIN_KEYPAD_C4, + TNETV107X_PIN_KEYPAD_C5, TNETV107X_PIN_KEYPAD_C6, -1 +}; + +static const short vlynq_pins[] = { + TNETV107X_PIN_VLYNQ_CLK, TNETV107X_PIN_VLYNQ_RXD0, + TNETV107X_PIN_VLYNQ_RXD1, + TNETV107X_PIN_VLYNQ_TXD0, TNETV107X_PIN_VLYNQ_TXD1, -1 +}; + +static const short lcd_pins[] = { + TNETV107X_PIN_LCD_AC_NCS, TNETV107X_PIN_LCD_HSYNC_RNW, + TNETV107X_PIN_LCD_VSYNC_A0, TNETV107X_PIN_LCD_PCLK_E, + TNETV107X_PIN_LCD_PD00, + TNETV107X_PIN_LCD_PD01, TNETV107X_PIN_LCD_PD02, TNETV107X_PIN_LCD_PD03, + TNETV107X_PIN_LCD_PD04, TNETV107X_PIN_LCD_PD05, TNETV107X_PIN_LCD_PD06, + TNETV107X_PIN_LCD_PD07, TNETV107X_PIN_LCD_PD08, TNETV107X_PIN_LCD_PD09, + TNETV107X_PIN_LCD_PD10, TNETV107X_PIN_LCD_PD11, TNETV107X_PIN_LCD_PD12, + TNETV107X_PIN_LCD_PD13, TNETV107X_PIN_LCD_PD14, TNETV107X_PIN_LCD_PD15, + TNETV107X_PIN_LCD_PD16_0, TNETV107X_PIN_LCD_PD17_0, + TNETV107X_PIN_LCD_PD18, + TNETV107X_PIN_LCD_PD19_1, TNETV107X_PIN_LCD_PD20_0, + TNETV107X_PIN_LCD_PD21_0, + TNETV107X_PIN_LCD_PD22_0, TNETV107X_PIN_LCD_PD23_0, -1 +}; + +static const short ssp_pins[] = { + TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2, + TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2, + TNETV107X_PIN_SSP1_3, -1 +}; + +static const short dummy[] = { -1 }; + +static const short *psc_pins[] = { + [TNETV107X_LPSC_ARM] = dummy, + [TNETV107X_LPSC_GEM] = dummy, + [TNETV107X_LPSC_DDR2_PHY] = dummy, + [TNETV107X_LPSC_TPCC] = dummy, + [TNETV107X_LPSC_TPTC0] = dummy, + [TNETV107X_LPSC_TPTC1] = dummy, + [TNETV107X_LPSC_RAM] = dummy, + [TNETV107X_LPSC_MBX_LITE] = dummy, + [TNETV107X_LPSC_LCD] = lcd_pins, + [TNETV107X_LPSC_ETHSS] = dummy, + [TNETV107X_LPSC_AEMIF] = dummy, + [TNETV107X_LPSC_CHIP_CFG] = dummy, + [TNETV107X_LPSC_TSC] = dummy, + [TNETV107X_LPSC_ROM] = dummy, + [TNETV107X_LPSC_UART2] = uart2_pins, + [TNETV107X_LPSC_PKTSEC] = dummy, + [TNETV107X_LPSC_SECCTL] = dummy, + [TNETV107X_LPSC_KEYMGR] = dummy, + [TNETV107X_LPSC_KEYPAD] = keypad_pins, + [TNETV107X_LPSC_GPIO] = dummy, + [TNETV107X_LPSC_MDIO] = dummy, + [TNETV107X_LPSC_SDIO0] = sdio0_pins, + [TNETV107X_LPSC_UART0] = uart0_pins, + [TNETV107X_LPSC_UART1] = uart1_pins, + [TNETV107X_LPSC_TIMER0] = dummy, + [TNETV107X_LPSC_TIMER1] = dummy, + [TNETV107X_LPSC_WDT_ARM] = dummy, + [TNETV107X_LPSC_WDT_DSP] = dummy, + [TNETV107X_LPSC_SSP] = ssp_pins, + [TNETV107X_LPSC_TDM0] = dummy, + [TNETV107X_LPSC_VLYNQ] = vlynq_pins, + [TNETV107X_LPSC_MCDMA] = dummy, + [TNETV107X_LPSC_USB0] = dummy, + [TNETV107X_LPSC_TDM1] = dummy, + [TNETV107X_LPSC_DEBUGSS] = dummy, + [TNETV107X_LPSC_ETHSS_RGMII] = dummy, + [TNETV107X_LPSC_SYSTEM] = dummy, + [TNETV107X_LPSC_IMCOP] = dummy, + [TNETV107X_LPSC_SPARE] = dummy, + [TNETV107X_LPSC_SDIO1] = sdio1_pins, + [TNETV107X_LPSC_USB1] = dummy, + [TNETV107X_LPSC_USBSS] = dummy, + [TNETV107X_LPSC_DDR2_EMIF1_VRST] = dummy, + [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = dummy, +}; + +const int psc_pins_size = sizeof(psc_pins) / sizeof(psc_pins[0]); + +int mux_select_pin(unsigned index) +{ + const struct pin_config *cfg; + unsigned long mask, mode, reg; + + if (index >= pin_table_size) + return 0; + + cfg = &pin_table[index]; + + mask = 0x1f << cfg->mask_offset; + mode = cfg->mode << cfg->mask_offset; + + reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index)); + reg = (reg & ~mask) | mode; + __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index)); + + return 1; +} + +int mux_select_pins(const short *pins) +{ + int i, ret = 1; + + for (i = 0; pins[i] >= 0; i++) + ret &= mux_select_pin(pins[i]); + + return ret; +} + +int mux_select_module(int lpsc) +{ + if (lpsc >= psc_pins_size) + return 0; + + return mux_select_pins(psc_pins[lpsc]); +} diff --git a/cpu/arm1176/tnetv107x/mon/mon_ssp.c b/cpu/arm1176/tnetv107x/mon/mon_ssp.c new file mode 100644 index 0000000..2efa260 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_ssp.c @@ -0,0 +1,235 @@ +/* + * Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs + * + * Copyright (C) 2009 Texas Instruments + * Written by Cyril Chemparathy cyril@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/clock.h> +#include <asm/arch/ssp.h> +#include <asm/arch/mux.h> + +#define SSP_PORT_CONFIG_MASK (SSP_EARLY_DIN | SSP_DELAY_DOUT) +#define SSP_PORT_CLKRATE_MASK 0x0f +#define SSP_SEQRAM_WR_EN (1 << 4) +#define SSP_SEQRAM_RD_EN (1 << 5) +#define SSP_START (1 << 15) +#define SSP_BUSY (1 << 10) +#define SSP_PORT_ASL (1 << 7) +#define SSP_PORT_CFO1 (1 << 6) +#define SSP_PREDIV 0xff +#define SSP_PORT_SEQRAM_SIZE 32 + +struct ssp_port_regs { + u32 conf2; + u32 addr; + u32 data; + u32 conf1; + u32 state; + u32 __pad[11]; +}; + +struct ssp_regs { + u32 rev_id; + u32 iosel1; + u32 iosel2; + u32 prediv; + u32 int_stat; + u32 int_en; + u32 test_ctrl; + u32 __pad[9]; + struct ssp_port_regs ports[2]; +}; + +static struct ssp_regs *ssp_regs = (struct ssp_regs *)TNETV107X_SSP_BASE; +static u32 *ssp_ram[2] = { + (u32 *)(TNETV107X_SSP_BASE + 0x100), + (u32 *)(TNETV107X_SSP_BASE + 0x180), +}; + +#define __ssp_reg_read(lev, reg) __raw_readl(&ssp_regs->reg) +#define __ssp_reg_write(lev, reg, val) __raw_writel(val, &ssp_regs->reg) +#define __ssp_reg_rmw(lev, reg, mask, val) \ + do { \ + u32 tmp; \ + tmp = __ssp_reg_read(lev+1, reg); \ + tmp = (tmp & ~(mask)) | val; \ + __ssp_reg_write(lev+1, reg, tmp); \ + } while (0) + +#define ssp_reg_clr(reg, mask) __ssp_reg_rmw(1, reg, mask, 0) +#define ssp_reg_set(reg, mask) __ssp_reg_rmw(1, reg, 0, mask) +#define ssp_reg_read(reg) __ssp_reg_read(0, reg) +#define ssp_reg_write(reg, val) __ssp_reg_write(0, reg, val) +#define ssp_reg_rmw(reg, mask, val) __ssp_reg_rmw(0, reg, mask, val) + +#define ssp_port_read(p, reg) ssp_reg_read(ports[p].reg) +#define ssp_port_write(p, reg, val) ssp_reg_write(ports[p].reg, val) +#define ssp_port_rmw(p, reg, m, v) ssp_reg_rmw(ports[p].reg, m, v) +#define ssp_port_set(p, reg, m) ssp_reg_set(ports[p].reg, m) +#define ssp_port_clr(p, reg, m) ssp_reg_clr(ports[p].reg, m) + +#define ssp_ram_read(p, ofs, val) __raw_readl(&ssp_ram[p][ofs]) +#define ssp_ram_write(p, ofs, val) __raw_writel(val, &ssp_ram[p][ofs]) + +static int initialized; + +void init_ssp(void) +{ + if (initialized) + return; + + clk_enable(TNETV107X_LPSC_SSP); + mux_select_module(TNETV107X_LPSC_SSP); + + /* Reset registers to a sensible known state */ + ssp_reg_write(iosel1, 0); + ssp_reg_write(iosel2, 0); + ssp_reg_write(int_en, 0); + ssp_reg_write(test_ctrl, 0); + ssp_port_write(0, conf1, SSP_PORT_ASL); + ssp_port_write(1, conf1, SSP_PORT_ASL); + ssp_port_write(0, conf2, SSP_PORT_CFO1); + ssp_port_write(1, conf2, SSP_PORT_CFO1); + + ssp_reg_rmw(prediv, 0xff, SSP_PREDIV); + + initialized = 1; +} + +void restore_ssp(void) +{ + init_ssp(); +} + +void suspend_ssp(void) +{ + clk_disable(TNETV107X_LPSC_SSP); + initialized = 0; +} + +int ssp_open(int port, u32 iosel, u32 config) +{ + u32 val; + + init_ssp(); + + /* IOSEL1 gets the least significant 16 bits + * of the device "iosel" field */ + val = ssp_reg_read(iosel1); + val &= 0xffff << (port ? 0 : 16); + val |= (iosel & 0xffff) << (port ? 16 : 0); + ssp_reg_write(iosel1, val); + + /* IOSEL2 gets the most significant 16 bits + * of the device "iosel" field */ + val = ssp_reg_read(iosel2); + val &= 0x0007 << (port ? 0 : 16); + val |= (iosel & 0x00070000) >> (port ? 0 : 16); + ssp_reg_write(iosel2, val); + + ssp_port_rmw(port, conf1, SSP_PORT_CONFIG_MASK, config); + + ssp_port_clr(port, conf2, SSP_PORT_CLKRATE_MASK); + + return 0; +} + +int ssp_close(int port) +{ + /* nothing for now */ + return 0; +} + +int ssp_load(int port, u32 *prog, int len) +{ + int i; + + if (!initialized) + return -EINVAL; + + if (len > SSP_PORT_SEQRAM_SIZE) + return -ENOSPC; + + /* Enable SeqRAM access */ + ssp_port_set(port, conf2, SSP_SEQRAM_WR_EN); + + /* Copy code */ + for (i = 0; i < len; i++) + ssp_ram_write(port, i, prog[i]); + + /* Disable SeqRAM access */ + ssp_port_clr(port, conf2, SSP_SEQRAM_WR_EN); + + return 0; +} + +int ssp_raw_read(int port) +{ + u32 val; + + if (!initialized) + return -EINVAL; + + val = ssp_reg_read(iosel2); + val >>= (port ? 27 : 11); + + return val & 0x0f; +} + +int ssp_raw_write(int port, u32 val) +{ + u32 mask; + + if (!initialized) + return -EINVAL; + + val &= 0x0f; + val <<= (port ? 22 : 6); + mask = 0x0f; + mask <<= (port ? 22 : 6); + ssp_reg_rmw(iosel2, mask, val); + + return 0; +} + +int ssp_run(int port, u32 pc, u32 input, u32 *output) +{ + if (!initialized) + return -EINVAL; + + if (pc & ~(0x3f)) + return -EINVAL; + + ssp_port_write(port, addr, input >> 16); + ssp_port_write(port, data, input & 0xffff); + ssp_port_rmw(port, conf1, 0x3f, pc); + + ssp_port_set(port, conf1, SSP_START); + + while (ssp_port_read(port, conf1) & SSP_BUSY) + ; + + if (output) + *(output) = (ssp_port_read(port, addr) << 16) | + (ssp_port_read(port, data) & 0xffff); + + /* return stop address */ + return ssp_port_read(port, state) & 0x3f; +} diff --git a/cpu/arm1176/tnetv107x/mon/mon_stubs.awk b/cpu/arm1176/tnetv107x/mon/mon_stubs.awk new file mode 100644 index 0000000..9093402 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_stubs.awk @@ -0,0 +1,101 @@ +# +# (C) Copyright 2009 +# Texas Instruments Inc., <www.ti.com> +# Cyril Chemparathy cyril@ti.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +BEGIN { + printf "/* Generated by monitor stub generation script, do not modify. */\n" > header; + printf "/* \n" >> header; + printf " * (C) Copyright 2009 \n" >> header; + printf " * Texas Instruments Inc., <www.ti.com> \n" >> header; + printf " * Cyril Chemparathy cyril@ti.com \n" >> header; + printf " * \n" >> header; + printf " * See file CREDITS for list of people who contributed to this \n" >> header; + printf " * project. \n" >> header; + printf " * \n" >> header; + printf " * This program is free software; you can redistribute it and/or \n" >> header; + printf " * modify it under the terms of the GNU General Public License as \n" >> header; + printf " * published by the Free Software Foundation; either version 2 of \n" >> header; + printf " * the License, or (at your option) any later version. \n" >> header; + printf " * \n" >> header; + printf " * This program is distributed in the hope that it will be useful, \n" >> header; + printf " * but WITHOUT ANY WARRANTY; without even the implied warranty of \n" >> header; + printf " * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the \n" >> header; + printf " * GNU General Public License for more details. \n" >> header; + printf " * \n" >> header; + printf " * You should have received a copy of the GNU General Public License \n" >> header; + printf " * along with this program; if not, write to the Free Software \n" >> header; + printf " * Foundation, Inc., 59 Temple Place, Suite 330, Boston, \n" >> header; + printf " * MA 02111-1307 USA \n" >> header; + printf " */ \n" >> header; + printf "#ifndef __MON_STUBS_DEFINES__\n" >> header; + printf "#define __MON_STUBS_DEFINES__\n\n" >> header; + + printf "/* Generated by monitor stub generation script, do not modify. */\n" > source; + printf "/* \n" >> source; + printf " * (C) Copyright 2009 \n" >> source; + printf " * Texas Instruments Inc., <www.ti.com> \n" >> source; + printf " * Cyril Chemparathy cyril@ti.com \n" >> source; + printf " * \n" >> source; + printf " * See file CREDITS for list of people who contributed to this \n" >> source; + printf " * project. \n" >> source; + printf " * \n" >> source; + printf " * This program is free software; you can redistribute it and/or \n" >> source; + printf " * modify it under the terms of the GNU General Public License as \n" >> source; + printf " * published by the Free Software Foundation; either version 2 of \n" >> source; + printf " * the License, or (at your option) any later version. \n" >> source; + printf " * \n" >> source; + printf " * This program is distributed in the hope that it will be useful, \n" >> source; + printf " * but WITHOUT ANY WARRANTY; without even the implied warranty of \n" >> source; + printf " * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the \n" >> source; + printf " * GNU General Public License for more details. \n" >> source; + printf " * \n" >> source; + printf " * You should have received a copy of the GNU General Public License \n" >> source; + printf " * along with this program; if not, write to the Free Software \n" >> source; + printf " * Foundation, Inc., 59 Temple Place, Suite 330, Boston, \n" >> source; + printf " * MA 02111-1307 USA \n" >> source; + printf " */ \n" >> source; + printf "#include "%s"\n\n", header >> source; +} + +($2 == "A") { + printf "#define mon%s_value 0x%s\n", $3, $1 >> header; + printf " .global mon%s\n", $3 >> source; + printf "mon%s:\n", $3 >> source; + printf " .word mon%s_value\n\n", $3 >> source; +} + +($2 == "T") && !($3 ~ "^__") && !($3 ~ "cache") && + !($3 == "printf") && !($3 == "raise") { + printf " .global %s\n", $3 >> source; + printf "%s:\n", $3 >> source; + printf " ldr ip, =mon_stack_end_value\n" >> source; + printf " stmdb ip!, {sp, lr}\n" >> source; + printf " mov sp, ip\n" >> source; + printf " ldr ip, =0x%s\n", $1 >> source; + printf " blx ip\n" >> source; + printf " ldmia sp, {sp, pc}\n\n" >> source; +} + +END { + printf "\n#endif /* __MON_STUBS_DEFINES__ */\n" >> header; +} diff --git a/cpu/arm1176/tnetv107x/mon/mon_timer.c b/cpu/arm1176/tnetv107x/mon/mon_timer.c new file mode 100644 index 0000000..96bd6a4 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_timer.c @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2009 + * Texas Instruments Inc., <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. philippe.robin@arm.com + * + * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> + +struct davinci_timer { + u_int32_t pid12; + u_int32_t emumgt; + u_int32_t na1; + u_int32_t na2; + u_int32_t tim12; + u_int32_t tim34; + u_int32_t prd12; + u_int32_t prd34; + u_int32_t tcr; + u_int32_t tgcr; + u_int32_t wdtcr; +}; + +struct davinci_timer *timer = + (struct davinci_timer *) CONFIG_SYS_TIMERBASE; + +#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) +#define TIM_CLK_DIV 16 + +static ulong timestamp; +static ulong lastinc; + +void init_timer(void) +{ + clk_enable(TNETV107X_LPSC_TIMER0); + + lastinc = timestamp = 0; + + /* We are using timer34 in unchained 32-bit mode, full speed */ + __raw_writel(0x0, &timer->tcr); + __raw_writel(0x0, &timer->tgcr); + __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr); + __raw_writel(0x0, &timer->tim34); + __raw_writel(TIMER_LOAD_VAL, &timer->prd34); + __raw_writel(2 << 22, &timer->tcr); +} + +void suspend_timer(void) +{ + clk_disable(TNETV107X_LPSC_TIMER0); +} + +void restore_timer(void) +{ + init_timer(); +} + +void reset_timer(void) +{ + lastinc = timestamp = 0; + + __raw_writel(0, &timer->tcr); + __raw_writel(0, &timer->tim34); + __raw_writel(2 << 22, &timer->tcr); +} + +static ulong get_timer_raw(void) +{ + ulong now = __raw_readl(&timer->tim34); + + if (now >= lastinc) { + /* normal mode */ + timestamp += now - lastinc; + } else { + /* overflow ... */ + timestamp += now + TIMER_LOAD_VAL - lastinc; + } + lastinc = now; + return timestamp; +} + +ulong get_timer(ulong base) +{ + return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void udelay(unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + tmo = CONFIG_SYS_HZ_CLOCK / 1000; + tmo *= usec; + tmo /= (1000 * TIM_CLK_DIV); + + endtime = get_timer_raw() + tmo; + + do { + ulong now = get_timer_raw(); + diff = endtime - now; + } while (diff >= 0); +} + +void mdelay(unsigned long msec) +{ + for (; msec; msec--) + udelay(1000); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/cpu/arm1176/tnetv107x/mon/mon_wdt.c b/cpu/arm1176/tnetv107x/mon/mon_wdt.c new file mode 100644 index 0000000..6868588 --- /dev/null +++ b/cpu/arm1176/tnetv107x/mon/mon_wdt.c @@ -0,0 +1,213 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, <www.ti.com> + * Cyril Chemparathy cyril@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> + +#define WDT_KICK_VALUE 1 +#define WDT_KICK_LOCK_STATE 0x3 +#define WDT_CHANGE_LOCK_STATE 0x3 +#define WDT_DISABLE_LOCK_STATE 0x3 +#define WDT_PRESCALE_LOCK_STATE 0x3 +#define WDT_MAX_PRESCALE_REG_VALUE 0xFFFF +#define WDT_MAX_CHANGE_REG_VALUE 0xFFFF +#define WDT_MAX_CLK_DIVISOR_VALUE 0xFFFE0001 +#define WDT_MIN_PRESCALE_REG_VALUE 0x0 +#define WDT_MIN_CHANGE_REG_VALUE 0x1 +#define WDT_KICK_LOCK_1ST_STAGE 0x5555 +#define WDT_KICK_LOCK_2ND_STAGE 0xAAAA +#define WDT_PRESCALE_LOCK_1ST_STAGE 0x5A5A +#define WDT_PRESCALE_LOCK_2ND_STAGE 0xA5A5 +#define WDT_CHANGE_LOCK_1ST_STAGE 0x6666 +#define WDT_CHANGE_LOCK_2ND_STAGE 0xBBBB +#define WDT_DISABLE_LOCK_1ST_STAGE 0x7777 +#define WDT_DISABLE_LOCK_2ND_STAGE 0xCCCC +#define WDT_DISABLE_LOCK_3RD_STAGE 0xDDDD + +struct wdt_regs { + u32 kick_lock; + u32 kick; + u32 change_lock; + u32 change; + u32 disable_lock; + u32 disable; + u32 prescale_lock; + u32 prescale; +}; + +static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE; + +#define wdt_reg_read(reg) __raw_readl(®s->reg) +#define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg) + +static int write_prescale_reg(unsigned long prescale_value) +{ + /* Unlocking 1st stage. */ + wdt_reg_write(prescale_lock, WDT_PRESCALE_LOCK_1ST_STAGE); + if ((wdt_reg_read(prescale_lock) & WDT_PRESCALE_LOCK_STATE) != 0x1) + return -1; + + /* Unlocking 2nd stage. */ + wdt_reg_write(prescale_lock, WDT_PRESCALE_LOCK_2ND_STAGE); + if ((wdt_reg_read(prescale_lock) & WDT_PRESCALE_LOCK_STATE) != 0x3) + return -1; + + wdt_reg_write(prescale, prescale_value); + + return 0; +} + +static int write_change_reg(unsigned long initial_timer_value) +{ + /* Unlocking 1st stage. */ + wdt_reg_write(change_lock, WDT_CHANGE_LOCK_1ST_STAGE); + if ((wdt_reg_read(change_lock) & WDT_CHANGE_LOCK_STATE) != 0x1) + return -1; + + /* Unlocking 2nd stage. */ + wdt_reg_write(change_lock, WDT_CHANGE_LOCK_2ND_STAGE); + if ((wdt_reg_read(change_lock) & WDT_CHANGE_LOCK_STATE) != 0x3) + return -1; + + wdt_reg_write(change, initial_timer_value); + + return 0; +} + +static int wdt_control(unsigned long disable_value) +{ + /* Unlocking 1st stage. */ + wdt_reg_write(disable_lock, WDT_DISABLE_LOCK_1ST_STAGE); + if ((wdt_reg_read(disable_lock) & WDT_DISABLE_LOCK_STATE) != 0x1) + return -1; + + /* Unlocking 2nd stage. */ + wdt_reg_write(disable_lock, WDT_DISABLE_LOCK_2ND_STAGE); + if ((wdt_reg_read(disable_lock) & WDT_DISABLE_LOCK_STATE) != 0x2) + return -1; + + /* Unlocking 3rd stage. */ + wdt_reg_write(disable_lock, WDT_DISABLE_LOCK_3RD_STAGE); + if ((wdt_reg_read(disable_lock) & WDT_DISABLE_LOCK_STATE) != 0x3) + return -1; + + wdt_reg_write(disable, disable_value); + return 0; +} + +static int wdt_set_period(unsigned long msec) +{ + unsigned long change_value, count_value; + unsigned long prescale_value = 1; + unsigned long refclk_khz, maxdiv; + int ret; + + refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM); + maxdiv = (WDT_MAX_CLK_DIVISOR_VALUE / refclk_khz); + + if ((!msec) || (msec > maxdiv)) + return -1; + + count_value = refclk_khz * msec; + if (count_value > WDT_MAX_CHANGE_REG_VALUE) { + change_value = count_value / WDT_MAX_PRESCALE_REG_VALUE + 1; + prescale_value = count_value / change_value; + } else { + change_value = count_value; + } + + ret = write_prescale_reg(prescale_value - 1); + if (ret) + return ret; + + ret = write_change_reg(change_value); + if (ret) + return ret; + + return 0; +} + +unsigned long last_wdt = -1; + +int wdt_start(unsigned long msecs) +{ + int ret; + ret = wdt_control(0); + if (ret) + return ret; + ret = wdt_set_period(msecs); + if (ret) + return ret; + ret = wdt_control(1); + if (ret) + return ret; + ret = wdt_kick(); + last_wdt = msecs; + return ret; +} + +int wdt_stop(void) +{ + last_wdt = -1; + return wdt_control(0); +} + +int wdt_kick(void) +{ + /* Unlocking 1st stage. */ + wdt_reg_write(kick_lock, WDT_KICK_LOCK_1ST_STAGE); + if ((wdt_reg_read(kick_lock) & WDT_KICK_LOCK_STATE) != 0x1) + return -1; + + /* Unlocking 2nd stage. */ + wdt_reg_write(kick_lock, WDT_KICK_LOCK_2ND_STAGE); + if ((wdt_reg_read(kick_lock) & WDT_KICK_LOCK_STATE) != 0x3) + return -1; + + wdt_reg_write(kick, WDT_KICK_VALUE); + return 0; +} + +void reset_cpu(ulong addr) +{ + wdt_start(1); + wdt_kick(); +} + +void init_wdt(void) +{ + clk_enable(TNETV107X_LPSC_WDT_ARM); +} + +void suspend_wdt(void) +{ + clk_disable(TNETV107X_LPSC_WDT_ARM); +} + +void resume_wdt(void) +{ + clk_enable(TNETV107X_LPSC_WDT_ARM); + if (last_wdt != -1) + wdt_start(last_wdt); +} diff --git a/include/asm-arm/arch-tnetv107x/clock.h b/include/asm-arm/arch-tnetv107x/clock.h new file mode 100644 index 0000000..1d8325a --- /dev/null +++ b/include/asm-arm/arch-tnetv107x/clock.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2008 Cyril Chemparathy, Texas Instruments, Inc. cyril@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0 +#define PSC_MDCTL_NEXT_SYNCRST 0x1 +#define PSC_MDCTL_NEXT_DISABLE 0x2 +#define PSC_MDCTL_NEXT_ENABLE 0x3 + +void mdelay(unsigned long msec); +unsigned long clk_get_rate(unsigned int clk); +long clk_round_rate(unsigned int clk, unsigned long hz); +int clk_set_rate(unsigned int clk, unsigned long hz); +int clk_get(unsigned int id); +void clk_enable(unsigned int id); +void clk_disable(unsigned int id); +void pinmux_enable(unsigned int id, int enable); +void lpsc_control(unsigned int id, u32 state); +int lpsc_status(unsigned int id); +void __lpsc_control(int nmod, int lrstz, ...); +void tnetv107x_init_clocks(unsigned long load_offset); + +#endif diff --git a/include/asm-arm/arch-tnetv107x/emif_defs.h b/include/asm-arm/arch-tnetv107x/emif_defs.h new file mode 100644 index 0000000..b8ed6b8 --- /dev/null +++ b/include/asm-arm/arch-tnetv107x/emif_defs.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _TNETV107X_EMIF_DEFS_H_ +#define _TNETV107X_EMIF_DEFS_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch-davinci/emif_defs.h> + +#endif diff --git a/include/asm-arm/arch-tnetv107x/hardware.h b/include/asm-arm/arch-tnetv107x/hardware.h new file mode 100644 index 0000000..e14ab4e --- /dev/null +++ b/include/asm-arm/arch-tnetv107x/hardware.h @@ -0,0 +1,300 @@ +/* + * Copyright (C) 2009 Cyril Chemparathy, Texas Instruments, Inc + * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc + * + * Based on hardware.h for DaVinci. Original Copyrights follow. + * + * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net + * + * Based on: linux/include/asm-arm/arch-davinci/hardware.h + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#ifndef __ASSEMBLY__ + +#include <asm/sizes.h> + +#define DIV_CEILING(num, den) ((((num)+(den)-1)/(den))-1) +#define DIV_FLOOR(num, den) (((num)/(den))-1) +#define ABS(x) (((x) < 0) ? -(x) : (x)) + +#define ASYNC_EMIF_PRESERVE -1 +struct async_emif_config { + unsigned mode; + unsigned select_strobe; + unsigned extend_wait; + unsigned wr_setup; + unsigned wr_strobe; + unsigned wr_hold; + unsigned rd_setup; + unsigned rd_strobe; + unsigned rd_hold; + unsigned turn_around; + enum { + ASYNC_EMIF_8 = 0, + ASYNC_EMIF_16 = 1, + ASYNC_EMIF_32 = 2, + } width; +}; + +struct ddr_emif_config { + enum { + SDRAM_TYPE_DDR2, + SDRAM_TYPE_DDR, + SDRAM_TYPE_SDR, + SDRAM_TYPE_MOBILE_SDR, + SDRAM_TYPE_MOBILE_DDR, + } type; + + /* control parameters */ + enum { + DDR2_TERM_NONE = 0, + DDR2_TERM_75_OHM = 1, + DDR2_TERM_150_OHM = 2, + DDR2_TERM_50_OHM = 3, + } ddr2_term; + enum { + SDRAM_DRIVE_NORMAL = 0, + SDRAM_DRIVE_HALF = 1, + SDRAM_DRIVE_FOURTH = 2, /* Mobile only */ + SDRAM_DRIVE_EIGHTH = 3, /* Mobile only */ + } drive; + enum { + DDR2_DDQS_SINGLE_ENDED = 0, + DDR2_DDQS_DIFFERENTIAL = 1, + } ddr2_ddqs; + enum { + SDRAM_PAGE_256_WORD = 0, + SDRAM_PAGE_512_WORD = 1, + SDRAM_PAGE_1024_WORD = 2, + SDRAM_PAGE_2048_WORD = 3, + } page_size; + + int ibank_pos; + int narrow_mode; + int ibank, ebank; + + /* timing parameters */ + unsigned t_rfc; /* 1/100 ns */ + unsigned t_rp; /* 1/100 ns */ + unsigned t_rcd; /* 1/100 ns */ + unsigned t_wr; /* 1/100 ns */ + unsigned t_ras; /* 1/100 ns */ + unsigned t_rc; /* 1/100 ns */ + unsigned t_rrd; /* 1/100 ns */ + unsigned t_xsnr; /* 1/100 ns */ + unsigned t_rtp; /* 1/100 ns */ + unsigned t_ras_max; /* ns */ + unsigned refresh_int; /* ns */ + unsigned t_xsrd; /* clocks */ + unsigned t_xp; /* clocks */ + unsigned t_aond; /* clocks */ + unsigned t_wtr; /* clocks */ + unsigned t_cke; /* clocks */ + unsigned cas_latency; /* 1/10 clocks */ + unsigned read_latency; /* clocks */ + unsigned pr_old_count; +}; + +/* Defined in linker script for monitor code */ +extern unsigned char _log_begin; +extern unsigned char _log_end; + +void init_plls(void); +void clk_delay(void); + +void init_log(void); +void log_char(unsigned char c); +void log_str(const char *str); +void log_number(unsigned long num, int base, int sign); +void log_clear(void); +void __printf(const char *fmt, ...); + +void init_ddr_emif(void); +void suspend_ddr_emif(void); +void restore_ddr_emif(void); + +void init_async_emif(void); +void suspend_async_emif(void); +void restore_async_emif(void); + +void init_timer(void); +void suspend_timer(void); +void restore_timer(void); + +void init_pmic(void); +void suspend_pmic(void); +void restore_pmic(void); + +void init_ssp(void); +void suspend_ssp(void); +void restore_ssp(void); + +void init_mdio(void); +void suspend_mdio(void); +void restore_mdio(void); + +void init_wdt(void); +void suspend_wdt(void); +void restore_wdt(void); + +int pmic_read(int reg); +int pmic_write(int reg, int val); +int pmic_get_core_voltage(void); +int pmic_set_core_voltage(int target_voltage); +void pmic_usb_set_enable(int enable); + +int mdio_read(char *name, unsigned char addr, + unsigned char reg, unsigned short *data); +int mdio_write(char *name, unsigned char addr, + unsigned char reg, unsigned short data); +int eth_hw_init(unsigned long mask0, unsigned long mask1); +int get_phy_id(int port); + +int wdt_start(unsigned long msecs); +int wdt_stop(void); +int wdt_kick(void); + +int clk_get(unsigned int id); + +void icache_invalidate(void); + +int eth_hw_init(unsigned long mask0, unsigned long mask1); + +#endif + +/* Chip configuration unlock codes and registers */ +#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38) +#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c) +#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4) +#define TNETV107X_KICK0_MAGIC 0x83e70b13 +#define TNETV107X_KICK1_MAGIC 0x95a4f1e0 + +/* Module base addresses */ +#define TNETV107X_TPCC_BASE 0x01C00000 +#define TNETV107X_TPTC0_BASE 0x01C10000 +#define TNETV107X_TPTC1_BASE 0x01C10400 +#define TNETV107X_INTC_BASE 0x03000000 +#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000 +#define TNETV107X_INTD_BASE 0x08038000 +#define TNETV107X_INTD_IPC_BASE 0x08038000 +#define TNETV107X_INTD_FAST_BASE 0x08039000 +#define TNETV107X_INTD_ASYNC_BASE 0x0803A000 +#define TNETV107X_INTD_SLOW_BASE 0x0803B000 +#define TNETV107X_PKA_BASE 0x08040000 +#define TNETV107X_RNG_BASE 0x08044000 +#define TNETV107X_TIMER0_BASE 0x08086500 +#define TNETV107X_TIMER1_BASE 0x08086600 +#define TNETV107X_WDT0_ARM_BASE 0x08086700 +#define TNETV107X_WDT1_DSP_BASE 0x08086800 +#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000 +#define TNETV107X_GPIO_BASE 0x08088000 +#define TNETV107X_UART1_BASE 0x08088400 +#define TNETV107X_TOUCHSCREEN_BASE 0x08088500 +#define TNETV107X_SDIO0_BASE 0x08088700 +#define TNETV107X_SDIO1_BASE 0x08088800 +#define TNETV107X_MDIO_BASE 0x08088900 +#define TNETV107X_KEYPAD_BASE 0x08088A00 +#define TNETV107X_SSP_BASE 0x08088C00 +#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000 +#define TNETV107X_PSC_BASE 0x0808B000 +#define TNETV107X_TDM0_BASE 0x08100000 +#define TNETV107X_TDM1_BASE 0x08100100 +#define TNETV107X_MCDMA_BASE 0x08108000 +#define TNETV107X_UART0_DMA_BASE 0x08108200 +#define TNETV107X_USBSS_BASE 0x08120000 +#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000 +#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 +#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000 +#define TNETV107X_IMCOP_BASE 0x01CC0000 +#define TNETV107X_MBX_LITE_BASE 0x07000000 +#define TNETV107X_ETHSS_BASE 0x0803C000 +#define TNETV107X_CPSW_BASE 0x0803C000 +#define TNETV107X_SPF_BASE 0x0803C800 +#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000 +#define TNETV107X_VTP_CNTRL_0 0x0803D800 +#define TNETV107X_VTP_CNTRL_1 0x0803D900 +#define TNETV107X_UART2_DMA_BASE 0x08108400 +#define TNETV107X_INTERNAL_MEMORY 0x20000000 +#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 +#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 +#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000 +#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 +#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000 +#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000 + +/* LPSC module definitions */ +#define TNETV107X_LPSC_ARM 0 +#define TNETV107X_LPSC_GEM 1 +#define TNETV107X_LPSC_DDR2_PHY 2 +#define TNETV107X_LPSC_TPCC 3 +#define TNETV107X_LPSC_TPTC0 4 +#define TNETV107X_LPSC_TPTC1 5 +#define TNETV107X_LPSC_RAM 6 +#define TNETV107X_LPSC_MBX_LITE 7 +#define TNETV107X_LPSC_LCD 8 +#define TNETV107X_LPSC_ETHSS 9 +#define TNETV107X_LPSC_AEMIF 10 +#define TNETV107X_LPSC_CHIP_CFG 11 +#define TNETV107X_LPSC_TSC 12 +#define TNETV107X_LPSC_ROM 13 +#define TNETV107X_LPSC_UART2 14 +#define TNETV107X_LPSC_PKTSEC 15 +#define TNETV107X_LPSC_SECCTL 16 +#define TNETV107X_LPSC_KEYMGR 17 +#define TNETV107X_LPSC_KEYPAD 18 +#define TNETV107X_LPSC_GPIO 19 +#define TNETV107X_LPSC_MDIO 20 +#define TNETV107X_LPSC_SDIO0 21 +#define TNETV107X_LPSC_UART0 22 +#define TNETV107X_LPSC_UART1 23 +#define TNETV107X_LPSC_TIMER0 24 +#define TNETV107X_LPSC_TIMER1 25 +#define TNETV107X_LPSC_WDT_ARM 26 +#define TNETV107X_LPSC_WDT_DSP 27 +#define TNETV107X_LPSC_SSP 28 +#define TNETV107X_LPSC_TDM0 29 +#define TNETV107X_LPSC_VLYNQ 30 +#define TNETV107X_LPSC_MCDMA 31 +#define TNETV107X_LPSC_USB0 32 +#define TNETV107X_LPSC_TDM1 33 +#define TNETV107X_LPSC_DEBUGSS 34 +#define TNETV107X_LPSC_ETHSS_RGMII 35 +#define TNETV107X_LPSC_SYSTEM 36 +#define TNETV107X_LPSC_IMCOP 37 +#define TNETV107X_LPSC_SPARE 38 +#define TNETV107X_LPSC_SDIO1 39 +#define TNETV107X_LPSC_USB1 40 +#define TNETV107X_LPSC_USBSS 41 +#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42 +#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43 +#define TNETV107X_LPSC_MAX 44 + +/* Interrupt controller */ +#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10) +#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500) +#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380) + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-tnetv107x/mux.h b/include/asm-arm/arch-tnetv107x/mux.h new file mode 100644 index 0000000..c5214d6 --- /dev/null +++ b/include/asm-arm/arch-tnetv107x/mux.h @@ -0,0 +1,307 @@ +/* + * Modified for TNETV107X U-Boot + * Copyright (C) 2009 Cyril Chemparathy <cyril@ti.com, Texas Instruments + * + * Table of the DAVINCI register configurations for the PINMUX combinations + * + * Author: Vladimir Barinov, MontaVista Software, Inc. + * Copyright (C) 2007-2008 MontaVista Software, Inc. source@mvista.com + * + * Based on linux/include/asm-arm/arch-omap/mux.h: + * Copyright (C) 2003 - 2005 Nokia Corporation + * Written by Tony Lindgren tony.lindgren@nokia.com + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_MUX_H +#define __ASM_ARCH_MUX_H + +struct pin_config { + unsigned char reg_index; + unsigned char mask_offset; + unsigned char mode; +}; + +#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \ + { reg, offset, mux_mode } + + +void chip_configuration_lock(int enable); +int mux_init(void); +int mux_select_pin(unsigned index); +int mux_select_pins(const short *pins); +int mux_select_module(int lpsc); + +enum tnetv107x_pin_mux_index { + TNETV107X_PIN_ASR_A00, + TNETV107X_PIN_GPIO32, + TNETV107X_PIN_ASR_A01, + TNETV107X_PIN_GPIO33, + TNETV107X_PIN_ASR_A02, + TNETV107X_PIN_GPIO34, + TNETV107X_PIN_ASR_A03, + TNETV107X_PIN_GPIO35, + TNETV107X_PIN_ASR_A04, + TNETV107X_PIN_GPIO36, + TNETV107X_PIN_ASR_A05, + TNETV107X_PIN_GPIO37, + TNETV107X_PIN_ASR_A06, + TNETV107X_PIN_GPIO38, + TNETV107X_PIN_ASR_A07, + TNETV107X_PIN_GPIO39, + TNETV107X_PIN_ASR_A08, + TNETV107X_PIN_GPIO40, + TNETV107X_PIN_ASR_A09, + TNETV107X_PIN_GPIO41, + TNETV107X_PIN_ASR_A10, + TNETV107X_PIN_GPIO42, + TNETV107X_PIN_ASR_A11, + TNETV107X_PIN_BOOT_STRP_0, + TNETV107X_PIN_ASR_A12, + TNETV107X_PIN_BOOT_STRP_1, + TNETV107X_PIN_ASR_A13, + TNETV107X_PIN_GPIO43, + TNETV107X_PIN_ASR_A14, + TNETV107X_PIN_GPIO44, + TNETV107X_PIN_ASR_A15, + TNETV107X_PIN_GPIO45, + TNETV107X_PIN_ASR_A16, + TNETV107X_PIN_GPIO46, + TNETV107X_PIN_ASR_A17, + TNETV107X_PIN_GPIO47, + TNETV107X_PIN_ASR_A18, + TNETV107X_PIN_GPIO48, + TNETV107X_PIN_SDIO1_DATA3_0, + TNETV107X_PIN_ASR_A19, + TNETV107X_PIN_GPIO49, + TNETV107X_PIN_SDIO1_DATA2_0, + TNETV107X_PIN_ASR_A20, + TNETV107X_PIN_GPIO50, + TNETV107X_PIN_SDIO1_DATA1_0, + TNETV107X_PIN_ASR_A21, + TNETV107X_PIN_GPIO51, + TNETV107X_PIN_SDIO1_DATA0_0, + TNETV107X_PIN_ASR_A22, + TNETV107X_PIN_GPIO52, + TNETV107X_PIN_SDIO1_CMD_0, + TNETV107X_PIN_ASR_A23, + TNETV107X_PIN_GPIO53, + TNETV107X_PIN_SDIO1_CLK_0, + TNETV107X_PIN_ASR_BA_1, + TNETV107X_PIN_GPIO54, + TNETV107X_PIN_SYS_PLL_CLK, + TNETV107X_PIN_ASR_CS0, + TNETV107X_PIN_ASR_CS1, + TNETV107X_PIN_ASR_CS2, + TNETV107X_PIN_TDM_PLL_CLK, + TNETV107X_PIN_ASR_CS3, + TNETV107X_PIN_ETH_PHY_CLK, + TNETV107X_PIN_ASR_D00, + TNETV107X_PIN_GPIO55, + TNETV107X_PIN_ASR_D01, + TNETV107X_PIN_GPIO56, + TNETV107X_PIN_ASR_D02, + TNETV107X_PIN_GPIO57, + TNETV107X_PIN_ASR_D03, + TNETV107X_PIN_GPIO58, + TNETV107X_PIN_ASR_D04, + TNETV107X_PIN_GPIO59_0, + TNETV107X_PIN_ASR_D05, + TNETV107X_PIN_GPIO60_0, + TNETV107X_PIN_ASR_D06, + TNETV107X_PIN_GPIO61_0, + TNETV107X_PIN_ASR_D07, + TNETV107X_PIN_GPIO62_0, + TNETV107X_PIN_ASR_D08, + TNETV107X_PIN_GPIO63_0, + TNETV107X_PIN_ASR_D09, + TNETV107X_PIN_GPIO64_0, + TNETV107X_PIN_ASR_D10, + TNETV107X_PIN_SDIO1_DATA3_1, + TNETV107X_PIN_ASR_D11, + TNETV107X_PIN_SDIO1_DATA2_1, + TNETV107X_PIN_ASR_D12, + TNETV107X_PIN_SDIO1_DATA1_1, + TNETV107X_PIN_ASR_D13, + TNETV107X_PIN_SDIO1_DATA0_1, + TNETV107X_PIN_ASR_D14, + TNETV107X_PIN_SDIO1_CMD_1, + TNETV107X_PIN_ASR_D15, + TNETV107X_PIN_SDIO1_CLK_1, + TNETV107X_PIN_ASR_OE, + TNETV107X_PIN_BOOT_STRP_2, + TNETV107X_PIN_ASR_RNW, + TNETV107X_PIN_GPIO29_0, + TNETV107X_PIN_ASR_WAIT, + TNETV107X_PIN_GPIO30_0, + TNETV107X_PIN_ASR_WE, + TNETV107X_PIN_BOOT_STRP_3, + TNETV107X_PIN_ASR_WE_DQM0, + TNETV107X_PIN_GPIO31, + TNETV107X_PIN_LCD_PD17_0, + TNETV107X_PIN_ASR_WE_DQM1, + TNETV107X_PIN_ASR_BA0_0, + TNETV107X_PIN_VLYNQ_CLK, + TNETV107X_PIN_GPIO14, + TNETV107X_PIN_LCD_PD19_0, + TNETV107X_PIN_VLYNQ_RXD0, + TNETV107X_PIN_GPIO15, + TNETV107X_PIN_LCD_PD20_0, + TNETV107X_PIN_VLYNQ_RXD1, + TNETV107X_PIN_GPIO16, + TNETV107X_PIN_LCD_PD21_0, + TNETV107X_PIN_VLYNQ_TXD0, + TNETV107X_PIN_GPIO17, + TNETV107X_PIN_LCD_PD22_0, + TNETV107X_PIN_VLYNQ_TXD1, + TNETV107X_PIN_GPIO18, + TNETV107X_PIN_LCD_PD23_0, + TNETV107X_PIN_SDIO0_CLK, + TNETV107X_PIN_GPIO19, + TNETV107X_PIN_SDIO0_CMD, + TNETV107X_PIN_GPIO20, + TNETV107X_PIN_SDIO0_DATA0, + TNETV107X_PIN_GPIO21, + TNETV107X_PIN_SDIO0_DATA1, + TNETV107X_PIN_GPIO22, + TNETV107X_PIN_SDIO0_DATA2, + TNETV107X_PIN_GPIO23, + TNETV107X_PIN_SDIO0_DATA3, + TNETV107X_PIN_GPIO24, + TNETV107X_PIN_EMU0, + TNETV107X_PIN_EMU1, + TNETV107X_PIN_RTCK, + TNETV107X_PIN_TRST_N, + TNETV107X_PIN_TCK, + TNETV107X_PIN_TDI, + TNETV107X_PIN_TDO, + TNETV107X_PIN_TMS, + TNETV107X_PIN_TDM1_CLK, + TNETV107X_PIN_TDM1_RX, + TNETV107X_PIN_TDM1_TX, + TNETV107X_PIN_TDM1_FS, + TNETV107X_PIN_KEYPAD_R0, + TNETV107X_PIN_KEYPAD_R1, + TNETV107X_PIN_KEYPAD_R2, + TNETV107X_PIN_KEYPAD_R3, + TNETV107X_PIN_KEYPAD_R4, + TNETV107X_PIN_KEYPAD_R5, + TNETV107X_PIN_KEYPAD_R6, + TNETV107X_PIN_GPIO12, + TNETV107X_PIN_KEYPAD_R7, + TNETV107X_PIN_GPIO10, + TNETV107X_PIN_KEYPAD_C0, + TNETV107X_PIN_KEYPAD_C1, + TNETV107X_PIN_KEYPAD_C2, + TNETV107X_PIN_KEYPAD_C3, + TNETV107X_PIN_KEYPAD_C4, + TNETV107X_PIN_KEYPAD_C5, + TNETV107X_PIN_KEYPAD_C6, + TNETV107X_PIN_GPIO13, + TNETV107X_PIN_TEST_CLK_IN, + TNETV107X_PIN_KEYPAD_C7, + TNETV107X_PIN_GPIO11, + TNETV107X_PIN_SSP0_0, + TNETV107X_PIN_SCC_DCLK, + TNETV107X_PIN_LCD_PD20_1, + TNETV107X_PIN_SSP0_1, + TNETV107X_PIN_SCC_CS_N, + TNETV107X_PIN_LCD_PD21_1, + TNETV107X_PIN_SSP0_2, + TNETV107X_PIN_SCC_D, + TNETV107X_PIN_LCD_PD22_1, + TNETV107X_PIN_SSP0_3, + TNETV107X_PIN_SCC_RESETN, + TNETV107X_PIN_LCD_PD23_1, + TNETV107X_PIN_SSP1_0, + TNETV107X_PIN_GPIO25, + TNETV107X_PIN_UART2_CTS, + TNETV107X_PIN_SSP1_1, + TNETV107X_PIN_GPIO26, + TNETV107X_PIN_UART2_RD, + TNETV107X_PIN_SSP1_2, + TNETV107X_PIN_GPIO27, + TNETV107X_PIN_UART2_RTS, + TNETV107X_PIN_SSP1_3, + TNETV107X_PIN_GPIO28, + TNETV107X_PIN_UART2_TD, + TNETV107X_PIN_UART0_CTS, + TNETV107X_PIN_UART0_RD, + TNETV107X_PIN_UART0_RTS, + TNETV107X_PIN_UART0_TD, + TNETV107X_PIN_UART1_RD, + TNETV107X_PIN_UART1_TD, + TNETV107X_PIN_LCD_AC_NCS, + TNETV107X_PIN_LCD_HSYNC_RNW, + TNETV107X_PIN_LCD_VSYNC_A0, + TNETV107X_PIN_LCD_MCLK, + TNETV107X_PIN_LCD_PD16_0, + TNETV107X_PIN_LCD_PCLK_E, + TNETV107X_PIN_LCD_PD00, + TNETV107X_PIN_LCD_PD01, + TNETV107X_PIN_LCD_PD02, + TNETV107X_PIN_LCD_PD03, + TNETV107X_PIN_LCD_PD04, + TNETV107X_PIN_LCD_PD05, + TNETV107X_PIN_LCD_PD06, + TNETV107X_PIN_LCD_PD07, + TNETV107X_PIN_LCD_PD08, + TNETV107X_PIN_GPIO59_1, + TNETV107X_PIN_LCD_PD09, + TNETV107X_PIN_GPIO60_1, + TNETV107X_PIN_LCD_PD10, + TNETV107X_PIN_ASR_BA0_1, + TNETV107X_PIN_GPIO61_1, + TNETV107X_PIN_LCD_PD11, + TNETV107X_PIN_GPIO62_1, + TNETV107X_PIN_LCD_PD12, + TNETV107X_PIN_GPIO63_1, + TNETV107X_PIN_LCD_PD13, + TNETV107X_PIN_GPIO64_1, + TNETV107X_PIN_LCD_PD14, + TNETV107X_PIN_GPIO29_1, + TNETV107X_PIN_LCD_PD15, + TNETV107X_PIN_GPIO30_1, + TNETV107X_PIN_EINT0, + TNETV107X_PIN_GPIO08, + TNETV107X_PIN_EINT1, + TNETV107X_PIN_GPIO09, + TNETV107X_PIN_GPIO00, + TNETV107X_PIN_LCD_PD20_2, + TNETV107X_PIN_TDM_CLK_IN_2, + TNETV107X_PIN_GPIO01, + TNETV107X_PIN_LCD_PD21_2, + TNETV107X_PIN_24M_CLK_OUT_1, + TNETV107X_PIN_GPIO02, + TNETV107X_PIN_LCD_PD22_2, + TNETV107X_PIN_GPIO03, + TNETV107X_PIN_LCD_PD23_2, + TNETV107X_PIN_GPIO04, + TNETV107X_PIN_LCD_PD16_1, + TNETV107X_PIN_USB0_RXERR, + TNETV107X_PIN_GPIO05, + TNETV107X_PIN_LCD_PD17_1, + TNETV107X_PIN_TDM_CLK_IN_1, + TNETV107X_PIN_GPIO06, + TNETV107X_PIN_LCD_PD18, + TNETV107X_PIN_24M_CLK_OUT_2, + TNETV107X_PIN_GPIO07, + TNETV107X_PIN_LCD_PD19_1, + TNETV107X_PIN_USB1_RXERR, + TNETV107X_PIN_ETH_PLL_CLK, + TNETV107X_PIN_MDIO, + TNETV107X_PIN_MDC, + TNETV107X_PIN_AIC_MUTE_STAT_N, + TNETV107X_PIN_TDM0_CLK, + TNETV107X_PIN_AIC_HNS_EN_N, + TNETV107X_PIN_TDM0_FS, + TNETV107X_PIN_AIC_HDS_EN_STAT_N, + TNETV107X_PIN_TDM0_TX, + TNETV107X_PIN_AIC_HNF_EN_STAT_N, + TNETV107X_PIN_TDM0_RX, +}; + +#endif diff --git a/include/asm-arm/arch-tnetv107x/nand_defs.h b/include/asm-arm/arch-tnetv107x/nand_defs.h new file mode 100644 index 0000000..46b8297 --- /dev/null +++ b/include/asm-arm/arch-tnetv107x/nand_defs.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net + * + * Parts shamelesly stolen from Linux Kernel source tree. + * + * ------------------------------------------------------------ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _NAND_DEFS_H_ +#define _NAND_DEFS_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/emif_defs.h> + +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE + +#define MASK_CLE 0x4000 +#define MASK_ALE 0x2000 + +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +extern void davinci_nand_init(struct nand_chip *nand); + +#endif diff --git a/include/asm-arm/arch-tnetv107x/ssp.h b/include/asm-arm/arch-tnetv107x/ssp.h new file mode 100644 index 0000000..a2bec2b --- /dev/null +++ b/include/asm-arm/arch-tnetv107x/ssp.h @@ -0,0 +1,79 @@ +/* + * Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs + * + * Copyright (C) 2009 Texas Instruments + * Written by Cyril Chemparathy cyril@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __SSP_H__ +#define __SSP_H__ + +/* + * Sequencer port IO pin configuration bits. These do not correlate 1-1 with + * the hardware. + * + * Note 1: The iosel field combines iosel1 and iosel2, and is therefore not a + * direct map to register space. It is best to use the macros below to + * construct iosel values. + * + * least significant 16 bits = iosel1, + * most significant 16 bits = iosel2 + */ + +#define SSP_IN 0x0000 +#define SSP_DATA 0x0001 +#define SSP_CLOCK 0x0002 +#define SSP_CHIPSEL 0x0003 +#define SSP_OUT 0x0004 +#define SSP_PIN_SEL(pin, v) ((v)<<((pin)*3)) +#define SSP_INPUT_SEL(pin) ((pin) << 16) + +/* Sequencer port config bits */ +#define SSP_EARLY_DIN (1 << 8) +#define SSP_DELAY_DOUT (1 << 9) + +/* Sequence map definitions */ +#define SSP_CLK_HIGH (1 << 0) +#define SSP_CLK_LOW (0 << 0) +#define SSP_DATA_HIGH (1 << 1) +#define SSP_DATA_LOW (0 << 1) +#define SSP_CS_HIGH (1 << 2) +#define SSP_CS_LOW (0 << 2) +#define SSP_IN_MODE (0 << 3) +#define SSP_OUT_MODE (1 << 3) +#define SSP_DATA_REG (1 << 4) +#define SSP_ADDR_REG (0 << 4) +#define SSP_OPCODE_DIRECT ((0x0) << 5) +#define SSP_OPCODE_TOGGLE ((0x1) << 5) +#define SSP_OPCODE_SHIFT ((0x2) << 5) +#define SSP_OPCODE_BRANCH0 ((0x4) << 5) +#define SSP_OPCODE_BRANCH1 ((0x5) << 5) +#define SSP_OPCODE_BRANCH ((0x6) << 5) +#define SSP_OPCODE_STOP ((0x7) << 5) +#define SSP_BRANCH(addr) ((addr)<<8) +#define SSP_COUNT(cycles) ((cycles)<<8) + +void init_ssp(void); +void resume_ssp(void); +void suspend_ssp(void); +int ssp_open(int port, u32 iosel, u32 config); +int ssp_close(int port); +int ssp_load(int port, u32 *prog, int len); +int ssp_raw_read(int port); +int ssp_raw_write(int port, u32 val); +int ssp_run(int port, u32 pc, u32 input, u32 *output); + +#endif /* __SSP_H__ */ diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index f04feae..7b4501d 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -40,6 +40,12 @@ #define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */ #define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */
+#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_PERIPORT_REMAP +#define CONFIG_PERIPORT_BASE 0x70000000 +#define CONFIG_PERIPORT_SIZE 0x13 + #define CONFIG_SYS_SDRAM_BASE 0x50000000
/* input clock of PLL: SMDK6400 has 12MHz input clock */ diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h new file mode 100644 index 0000000..fcc969c --- /dev/null +++ b/include/configs/tnetv107x_evm.h @@ -0,0 +1,361 @@ +/* + * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com> + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +#define CONFIG_SYS_USE_NAND +#define CONFIG_SYS_UBOOT_BASE TEXT_BASE +#define CONFIG_DISABLE_TCM +#define CONFIG_PERIPORT_REMAP +#define CONFIG_PERIPORT_BASE 0x2000000 +#define CONFIG_PERIPORT_SIZE 0x10 + +/*========*/ +/* System */ +/*========*/ + +#undef CONFIG_SYS_USE_NET +#undef CONFIG_SYS_USE_USB +#define CONFIG_SYS_MON_DEBUG + +#include <asm/arch/hardware.h> + +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM1176 +#define CONFIG_TNETV107X +#define CONFIG_SYS_CLK_FREQ clk_get(TNETV107X_LPSC_ARM) +#define CONFIG_SYS_INT_OSC_FREQ 24000000 + +/* SYS PLL Configuration */ +#define CONFIG_PLL_SYS_INT_OSC 1 +#define CONFIG_PLL_SYS_PLL_FREQ 400000000 +#define CONFIG_PLL_SYS_EXT_FREQ 25000000 +#define CONFIG_PLL_SYS_ARM1176_CLK 400000000 +#define CONFIG_PLL_SYS_DSP_CLK 400000000 +#define CONFIG_PLL_SYS_DDR_CLK 400000000 +#define CONFIG_PLL_SYS_FULL_CLK 200000000 +#define CONFIG_PLL_SYS_LCD_CLK 100000000 +#define CONFIG_PLL_SYS_VLYNQ_REF_CLK 100000000 +#define CONFIG_PLL_SYS_TSC_CLK 1470000 +#define CONFIG_PLL_SYS_HALF_CLK 100000000 + +/* TDM PLL Configuration */ +#define CONFIG_PLL_TDM_CONFIG 0 +#define CONFIG_PLL_TDM_INT_OSC 1 +#define CONFIG_PLL_TDM_PLL_FREQ 40960000 +#define CONFIG_PLL_TDM_EXT_FREQ 19200000 +#define CONFIG_PLL_TDM_TDM0_CLK 8192000 +#define CONFIG_PLL_TDM_TIMER_CLK 40960000 +#define CONFIG_PLL_TDM_TDM1_CLK 8192000 + +/* ETH PLL Configuration */ +#define CONFIG_PLL_ETH_CONFIG 1 +#define CONFIG_PLL_ETH_INT_OSC 1 +#define CONFIG_PLL_ETH_PLL_FREQ 500000000 +#define CONFIG_PLL_ETH_EXT_FREQ 25000000 +#define CONFIG_PLL_ETH_5_CLK 5000000 +#define CONFIG_PLL_ETH_50_CLK 50000000 +#define CONFIG_PLL_ETH_125_CLK 125000000 +#define CONFIG_PLL_ETH_250_CLK 250000000 +#define CONFIG_PLL_ETH_25_CLK 25000000 + +/* DDR EMIF Configuration */ +#define DDR_EMIF_TYPE SDRAM_TYPE_DDR2 +#define DDR_EMIF_TERM DDR2_TERM_NONE +#define DDR_EMIF_DRIVE SDRAM_DRIVE_NORMAL +#define DDR_EMIF_DDQS DDR2_DDQS_DIFFERENTIAL +#define DDR_EMIF_IBANK_POS 0 +#define DDR_EMIF_NARROW_MODE 1 +#define DDR_EMIF_IBANK 3 +#define DDR_EMIF_EBANK 0 +#define DDR_EMIF_PAGE_SIZE SDRAM_PAGE_1024_WORD +#define DDR_EMIF_T_RFC 12750 /* 1/100 ns */ +#define DDR_EMIF_T_RP 1500 /* 1/100 ns */ +#define DDR_EMIF_T_RCD 1500 /* 1/100 ns */ +#define DDR_EMIF_T_WR 1500 /* 1/100 ns */ +#define DDR_EMIF_T_RAS 4500 /* 1/100 ns */ +#define DDR_EMIF_T_RC 6000 /* 1/100 ns */ +#define DDR_EMIF_T_RRD 1000 /* 1/100 ns */ +#define DDR_EMIF_T_XSNR 13750 /* 1/100 ns */ +#define DDR_EMIF_T_RTP 750 /* 1/100 ns */ +#define DDR_EMIF_T_RAS_MAX 70000 /* ns */ +#define DDR_EMIF_REFRESH_INT 7800 /* ns */ +#define DDR_EMIF_T_XSRD 200 /* clocks */ +#define DDR_EMIF_T_XP 2 /* clocks */ +#define DDR_EMIF_T_AOND 2 /* clocks */ +#define DDR_EMIF_T_WTR 2 /* clocks */ +#define DDR_EMIF_T_CKE 3 /* clocks */ +#define DDR_EMIF_CAS_LATENCY 40 /* 1/10 clocks */ +#define DDR_EMIF_READ_LATENCY (DDR_EMIF_CAS_LATENCY/10 + 2) +#define DDR_EMIF_PR_OLD_COUNT 0x18 + +/* Async EMIF Configuration */ +#define ASYNC_EMIF_MODE_NOR 0 +#define ASYNC_EMIF_MODE_NAND 1 +#define ASYNC_EMIF_MODE_ONENAND 2 + +#define ASYNC_EMIF_CS0_SELECT_STROBE 0 +#define ASYNC_EMIF_CS0_EXTEND_WAIT 0 +#define ASYNC_EMIF_CS0_WR_SETUP 5 /* cycles */ +#define ASYNC_EMIF_CS0_WR_STROBE 5 /* cycles */ +#define ASYNC_EMIF_CS0_WR_HOLD 2 /* cycles */ +#define ASYNC_EMIF_CS0_RD_SETUP 5 /* cycles */ +#define ASYNC_EMIF_CS0_RD_STROBE 5 /* cycles */ +#define ASYNC_EMIF_CS0_RD_HOLD 2 /* cycles */ +#define ASYNC_EMIF_CS0_TURN_AROUND 5 /* cycles */ +#define ASYNC_EMIF_CS0_WIDTH 0 + +#define ASYNC_EMIF_CS1_SELECT_STROBE 0 +#define ASYNC_EMIF_CS1_EXTEND_WAIT 0 +#define ASYNC_EMIF_CS1_WR_SETUP 2 /* cycles */ +#define ASYNC_EMIF_CS1_WR_STROBE 27 /* cycles */ +#define ASYNC_EMIF_CS1_WR_HOLD 4 /* cycles */ +#define ASYNC_EMIF_CS1_RD_SETUP 2 /* cycles */ +#define ASYNC_EMIF_CS1_RD_STROBE 27 /* cycles */ +#define ASYNC_EMIF_CS1_RD_HOLD 4 /* cycles */ +#define ASYNC_EMIF_CS1_TURN_AROUND 2 /* cycles */ +#define ASYNC_EMIF_CS1_WIDTH ASYNC_EMIF_PRESERVE + +#define ASYNC_EMIF_CS2_SELECT_STROBE 0 +#define ASYNC_EMIF_CS2_EXTEND_WAIT 0 +#define ASYNC_EMIF_CS2_WR_SETUP 2 /* cycles */ +#define ASYNC_EMIF_CS2_WR_STROBE 27 /* cycles */ +#define ASYNC_EMIF_CS2_WR_HOLD 4 /* cycles */ +#define ASYNC_EMIF_CS2_RD_SETUP 2 /* cycles */ +#define ASYNC_EMIF_CS2_RD_STROBE 27 /* cycles */ +#define ASYNC_EMIF_CS2_RD_HOLD 4 /* cycles */ +#define ASYNC_EMIF_CS2_TURN_AROUND 2 /* cycles */ +#define ASYNC_EMIF_CS2_WIDTH ASYNC_EMIF_PRESERVE + +#define ASYNC_EMIF_CS3_SELECT_STROBE 0 +#define ASYNC_EMIF_CS3_EXTEND_WAIT 0 +#define ASYNC_EMIF_CS3_WR_SETUP 1 /* cycles */ +#define ASYNC_EMIF_CS3_WR_STROBE 90 /* cycles */ +#define ASYNC_EMIF_CS3_WR_HOLD 3 /* cycles */ +#define ASYNC_EMIF_CS3_RD_SETUP 1 /* cycles */ +#define ASYNC_EMIF_CS3_RD_STROBE 26 /* cycles */ +#define ASYNC_EMIF_CS3_RD_HOLD 3 /* cycles */ +#define ASYNC_EMIF_CS3_TURN_AROUND 1 /* cycles */ +#define ASYNC_EMIF_CS3_WIDTH 0 + +#define CONFIG_SYS_TIMERBASE TNETV107X_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(TNETV107X_LPSC_TIMER0) +#define CONFIG_SYS_HZ 1000 +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT + +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define PHYS_SDRAM_1 TNETV107X_DDR_EMIF_DATA_BASE +#define PHYS_SDRAM_1_SIZE 0x04000000 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_STACKSIZE (256*1024) + +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 TNETV107X_UART1_BASE +#define CONFIG_SYS_NS16550_CLK clk_get(TNETV107X_LPSC_UART1) +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#if defined(CONFIG_SYS_USE_NET) +#define CONFIG_DRIVER_TI_CPSW3G +#define CONFIG_MII +#define CONFIG_PHY_GIGE +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#else +#endif + +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#ifdef CONFIG_SYS_USE_NAND +#undef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_NAND_DAVINCI +#define CONFIG_ENV_SIZE (SZ_128K) +#define CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_NAND_1BIT_ECC +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE +#define CONFIG_SYS_CLE_MASK 0x10 +#define CONFIG_SYS_ALE_MASK 0x8 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define NAND_MAX_CHIPS 1 +#define CONFIG_ENV_OFFSET 0x180000 +#define DEF_BOOTM "" +#define MTDIDS_DEFAULT \ + "nand0=davinci_nand.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=davinci_nand.0:1536k(uboot)ro,128k(params)ro,4m(kernel),-(filesystem)" +#endif + +#ifdef CONFIG_SYS_USE_NOR +#define CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_SECT_SZ 0x20000 +#define PHYS_FLASH_SIZE 0x4000000 +#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 4) +#define CONFIG_SYS_FLASH_BASE TNETV107X_ASYNC_EMIF_DATA_CE1_BASE +#define CONFIG_SYS_MAX_FLASH_SECT \ + (PHYS_FLASH_SIZE / CONFIG_SYS_FLASH_SECT_SZ) +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ +#define CONFIG_FLASH_SHOW_PROGRESS 50 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +/*==============================*/ +/* USB Configuration */ +/*==============================*/ +#ifdef CONFIG_SYS_USE_USB +#define CONFIG_MUSB +#define CONFIG_USB_TNETV107X +#define CONFIG_USB_STORAGE +#endif + +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ +#undef CONFIG_MISC_INIT_R +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_SYS_PROMPT "U-Boot > " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LOAD_ADDR \ + (CONFIG_SYS_MEMTEST_START + 0x700000) + +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR \ + (CONFIG_SYS_MEMTEST_START + 0x100) +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS \ + "mem=32M console=ttyS1,115200n8 root=/dev/mmcblk0p1 rw noinitrd" +#define CONFIG_BOOTCOMMAND "" +#define CONFIG_BOOTDELAY 3 + +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#undef CONFIG_CMD_DIAG +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_EEPROM + +#ifdef CONFIG_SYS_USE_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#else +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_PING +#endif + +#ifdef CONFIG_SYS_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#endif + +#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_SYS_USE_NOR) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_SIZE SZ_16K +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_ENV +#endif + +#ifdef CONFIG_SYS_USE_USB +#define CONFIG_CMD_USB +#define CONFIG_CMD_STORAGE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#else +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_STORAGE +#undef CONFIG_CMD_FAT +#undef CONFIG_CMD_EXT2 +#undef CONFIG_DOS_PARTITION +#endif + +#endif /* __CONFIG_H */