On 13.02.2019, at 21:19, Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
Am 13.02.2019 um 21:13 schrieb Heinrich Schuchardt:
The SPL image for the rk3288 boards has to fit into 32 KiB. This includes 4 KiB for the device tree and up to 2 KiB for the file header.
I'm not related to this board (and don't mean to step against this patch), but I have similar problems on socfpga (though with 64 KiB, not 32 KiB) and trying to solve them, so:
How do you know the DTB is 4 KiB maximum? Is there a check for this?
Aside from that, I don't know how it is for rk3288, but socfpga allocates initial stack, heap and 'gd' into the same RAM, so available size check should also substract that from my 64 KiB. How is this handled here?
The RK3288 has ~ 100kB of SRAM, but the BootROM has a size limitation on loading the SPL stage. So stack will always be located beyond the end of the SPL.
Regards, Simon
Without the patch we missed to see that the TinkerBoard spl/u-boot-spl-dtb.bin file is too big. Signed-off-by: Heinrich Schuchardt xypron.glpk@gmx.de
include/configs/rk3288_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index c59f5eff7a..7c8d01ec50 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -23,6 +23,8 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 +/* 32 KiB - 4 KiB for dtb - 2 KiB for file header */ +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x1800) #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) # define CONFIG_SPL_TEXT_BASE 0x0 #else
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