I fear this is not as easy as flipping a bit in a register. Depending on the platform caches tend to be tied to the MMU, so enabling the caches require setting up correct data structures for the MMU to work. That's the non-trivial work.
Not that difficult, either. You just need to fill the top-level page table for 1MB sections (4096 sections = 16k bytes, which must be aligned on a 16k boundary).
Apart from that, there is CONFIG_CMD_CACHE which builds common/cmd_cache.c. I see that at least two PXA250 platforms enable this, so maybe simply try that?
I think it's always disabled on arm, for the mmu reason.
Maybe you can reap the code from their repository. If you do, please post it here ;)
Or I can cook an RFC patch later, after redoing the 8815 patches. I was just considering trying it these days, as I've done the same on another straight-on-iron project and it's not that difficult.
/alessandro