Hello!
I suspect that there is a bug in board/freescale/p1_p2_rdb_pc/tlb.c code which configures TLB entry for initial L2 SRAM.
When L2 is 512 kB long (e.g. on P2020) then U-Boot *unsets* MAS2_I bit for first half of L2 and for second half of L2 U-Boot *sets* this bit.
See code: https://source.denx.de/u-boot/u-boot/-/blob/v2022.04/board/freescale/p1_p2_r...
I do not think that one part of L2 SRAM should be configured differently as second part. Therefore I think that this is a bug in U-Boot code.
Do you know is correct configuration of TLB entries for initial L2 SRAM?
MAS2_I is Caching-inhibited bit which is described as:
Caching-inhibited: * 0 - Accesses to this page are considered cacheable. * 1 - The page is considered caching-inhibited. All loads and stores to the page bypass the caches and are performed directly to main memory. A read or write to a caching-inhibited page affects only the memory element specified by the operation.