Hi,
On 19/12/16 10:01, Maxime Ripard wrote:
On Mon, Dec 19, 2016 at 01:50:09AM +0000, Andre Przywara wrote:
According to Jens disabling the on-die-termination should set bit 5, not bit 1 in the respective register. Fix this.
Reported-by: Jens Kuske jenskuske@gmail.com Signed-off-by: Andre Przywara andre.przywara@arm.com
arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c index 6ee73ae..1bdd738 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c @@ -438,7 +438,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) | (0x1 << 1) | (0x3 << 2) | (0x3 << 12) | (0x3 << 14),
IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x20);You should use a define here if that bit function is known.
I agree, and I tried but I failed to find one. That part seems to differ from the Keystone documentation, which doesn't know an ODT _dis_able bit at all.
Maybe Jens can add his source?
Cheers, Andre.