The BAR0/BAR1 is not used by RC, but it may affect the space allocate during RC scan.
Signed-off-by: Jon Lin jon.lin@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
drivers/pci/pcie_dw_rockchip.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 6da618055cb..0091fb62bae 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -64,6 +64,8 @@ struct rk_pcie { /* Parameters for the waiting for #perst signal */ #define MACRO_US 1000
+#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 + static int rk_pcie_read(void __iomem *addr, int size, u32 *val) { if ((uintptr_t)addr & (size - 1)) { @@ -210,6 +212,17 @@ static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); }
+static void rk_pcie_disable_bar01(struct rk_pcie *pci) +{ + dw_pcie_dbi_write_enable(&pci->dw, true); + + /* Disable BAR0 BAR1 */ + writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4); + writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4); + + dw_pcie_dbi_write_enable(&pci->dw, false); +} + static int is_link_up(struct rk_pcie *priv) { u32 val; @@ -331,6 +344,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) /* Set RC mode */ rk_pcie_writel_apb(priv, 0x0, 0xf00040); pcie_dw_setup_host(&priv->dw); + rk_pcie_disable_bar01(priv);
ret = rk_pcie_link_up(priv, priv->gen); if (ret < 0)