Re: [U-Boot] [PATCH v2 1/8] spi: cadence_qspi: Fix clearing of pol/pha bits

On 11/25/2016 03:38 PM, Phil Edworthy wrote:

Or'ing together bit positions is clearly wrong.

Signed-off-by: Phil Edworthy phil.edworthy@renesas.com

drivers/spi/cadence_qspi_apb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e285d3c..2403e71 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -311,8 +311,8 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base,

cadence_qspi_apb_controller_disable(reg_base); reg = readl(reg_base + CQSPI_REG_CONFIG);

• reg &= ~(1 <<

• (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
  

• reg &= ~(1 << CQSPI_REG_CONFIG_CLK_POL_LSB);
• reg &= ~(1 << CQSPI_REG_CONFIG_CLK_PHA_LSB);

Oh, nice.

Acked-by: Marek Vasut marek.vasut@gmail.com

reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);