Hi Simon,
On Sat, Mar 11, 2023 at 7:33 AM Simon Glass sjg@chromium.org wrote:
At present U-Boot no longer builds as a complete rom for minnowmaxs since it is too big for the section.
Adjust CONFIG_TEXT_BASE and CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Add documentation on how to make this change safely.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Add new patch which boots while still enabling EFI_LOADER
Thanks for working on this!
arch/x86/dts/minnowmax.dts | 2 +- configs/minnowmax_defconfig | 3 ++- doc/board/intel/minnowmax.rst | 15 +++++++++++++-- 3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 68e0510c68d..466309f2b8d 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -206,7 +206,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache";
reg = <0x006f0000 0x00010000>;
reg = <0x005f0000 0x00010000>; }; }; };diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index b3b15d86e17..b93c0d729f8 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_TEXT_BASE=0xFFF00000 +CONFIG_TEXT_BASE=0xFFE00000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x6EF000 @@ -18,6 +18,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/doc/board/intel/minnowmax.rst b/doc/board/intel/minnowmax.rst index 1ba25b50d21..db20d966f06 100644 --- a/doc/board/intel/minnowmax.rst +++ b/doc/board/intel/minnowmax.rst @@ -55,8 +55,8 @@ Offset Description Controlling config 001000 me.bin Set by the descriptor 500000 <spare> 6ef000 Environment CONFIG_ENV_OFFSET
This should be moved to after u-boot-dtb.bin
-6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE -700000 u-boot-dtb.bin CONFIG_TEXT_BASE +5f0000 MRC cache CONFIG_ENABLE_MRC_CACHE +600000 u-boot-dtb.bin CONFIG_TEXT_BASE 7b0000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR 7f8000 <spare> (depends on size of fsp.bin) @@ -68,3 +68,14 @@ Overall ROM image size is controlled by CONFIG_ROM_SIZE. Note that the debug version of the FSP is bigger in size. If this version is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of the default value 0xfffc0000.
+If you want to change CONFIG_TEXT_BASE from the current value of 0x600000
CONFIG_TEXT_BASE is now 0xFFE00000 but not 0x600000.
+you need to check a few other things. CONFIG_SYS_MONITOR_BASE should +automatically update to be the same as CONFIG_TEXT_BASE but +CONFIG_SYS_MONITOR_LEN may need to be adjusted too. It must cover the space +from the start of U-Boot to the end of the RAM, since the 16-bit boot needs to +be able to jump to U-Boot. See the end of arch/x86/lib/fsp1/fsp_car.S which +has these values.
+Also check the MRC cache address in the devicetree ("rw-mrc-cache"). It must
+not overlap with U-Boot.
Regards, Bin