Hello!
In my customized PCI initialization (within a set of tests), I do the following: (...) immap->im_siu_conf.sc_ppc_alrh = 0x61207893; immap->im_siu_conf.sc_ppc_acr = 0x6;
immap->im_memctl.memc_pcimsk0 = 0xfffc0000; immap->im_memctl.memc_pcibr0 = 0x80000001;
immap->im_pci.pci_pitar0 = 0x00000000; /* PCI base */ immap->im_pci.pci_pibar0 = 0x00000000; /* Local base */ /* 64KB address space, no snooping, no prefetch */ immap->im_pci.pci_picmr0 = cpu_to_le32(0xFFFF0000); bdf = PCI_BDF(0, 0x17, 0); pci_read_config_dword(bdf, PCI_COMMAND, &temp32); pci_write_config_dword(bdf, PCI_COMMAND, temp32 | 0x06); /* Set inbound transactions region base address */ pci_write_config_dword(bdf, 0x10, 0x80000000); /* Set latency and cache size */ pci_write_config_byte(bdf, PCI_CACHE_LINE_SIZE, 0x08); pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0xF8);
bdf = PCI_BDF(0, 0x16, 0); pci_read_config_dword(bdf, PCI_COMMAND, &temp32); pci_write_config_dword(bdf, PCI_COMMAND, temp32 | 0x06); /* Set inbound transactions region base address */ pci_write_config_dword(bdf, 0x10, (0x80000000 + 0x00010000)); /* Set latency and cache size */ pci_write_config_byte(bdf, PCI_CACHE_LINE_SIZE, 0x08); pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0xF8);
bdf = PCI_BDF(0, 0x18, 0); pci_read_config_dword(bdf, PCI_COMMAND, &temp32); pci_write_config_dword(bdf, PCI_COMMAND, temp32 | 0x06); /* Set inbound transactions region base address */ pci_write_config_dword(bdf, 0x10, (0x80000000 + 0x00020000)); /* Set latency and cache size */ pci_write_config_byte(bdf, PCI_CACHE_LINE_SIZE, 0x08); pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0xF8);
/* Set CPU bridge as slave */ pci_hose_read_config_dword (hose, host_devno, PCI_COMMAND, &temp32); pci_hose_write_config_dword (hose, host_devno, PCI_COMMAND, temp32 | 0x02); /* Set outbound transactions region base address */ pci_hose_write_config_dword (hose, host_devno, 0x10, CFG_IMMR); /* Set latency and cache size */ pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE, 0x08); pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER, 0xF8);
immap->im_siu_conf.sc_ppc_alrh = 0x30126789; immap->im_siu_conf.sc_ppc_acr = 0x03; (...)
And I am using readl and writel to read and write to/from the PCI memory address space. But, for some reason, I can't access properly (reads and writes) the devices that I configured earlier. What am I doing wrong? Or the PCI configurations are not correct? (In linux I can access those devices!...)
Thank you! Filipe.