Dear Prabhakar Kushwaha,
In message 1329296055-28541-1-git-send-email-prabhakar@freescale.com you wrote:
Update the NOR code base to support NOR-boot debugging. It ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be valid fetchable OP code address.
While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared and the processor tries to fetch an instruction from the debug exception vector (IVPR|IVOR15); since now we are in AS=0, the application needs to ensure the proper configuration to have IVOR|IVOR15 accessible from AS=0 also.
Signed-off-by: Radu Lazarescu radu.lazarescu@freescale.com Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com
...
- _mas0 = MAS0_TLBSEL(1) |
MAS0_ESEL(CONFIG_DEBUGGER_TEMP_TLB);
You are using an undocumented CONFIG_ option here.
+++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -184,6 +184,48 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b
+#if defined(CONFIG_E500_V1_V2) && !defined(CONFIG_SYS_RAMBOOT)
What if no such debug support is needed, and code size hurts?
@@ -107,6 +107,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_DEBUGGER_TEMP_TLB 3
Undocumented!
Best regards,
Wolfgang Denk