The default timer rate may be different than 25 MHz, permit overriding the default rate in board configuration file. Ultimatelly, this should be properly handled by a clock driver, however that is not available on Gen5 yet.
Signed-off-by: Marek Vasut marex@denx.de Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com --- V2: Drop misleading comment --- include/configs/socfpga_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8d10469e7c..54a43569dc 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -94,12 +94,13 @@ * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER -/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#ifndef CONFIG_SYS_TIMER_RATE #define CONFIG_SYS_TIMER_RATE 25000000 #endif +#endif
/* * L4 Watchdog