On Jul 20, 2011, at 9:47 AM, Stephen George wrote:
Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR.
Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required.
Signed-off-by: Stephen George stephen.george@freescale.com
arch/powerpc/cpu/mpc85xx/cpu_init.c | 11 +++++++++++ arch/powerpc/include/asm/immap_85xx.h | 7 ++++++- board/freescale/corenet_ds/law.c | 3 ++- 3 files changed, 19 insertions(+), 2 deletions(-)
in the future:
1. when posting upstream (reset internal counter [v3]) 2. don't CC internal list 3. dont need [upstream] in the subject
- k