This is a slight difference in emif_ddr_phy_status register offsets for DRA7xx EMIF and older versions. And ecc registers are available only in DRA7xx EMIC. Add support for this difference and ecc registers.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/emif.h | 17 ++++++++++++++++- arch/arm/mach-omap2/emif-common.c | 6 +++--- 2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 9a46340deb..a661ba9032 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -664,12 +664,27 @@ struct emif_reg_struct { u32 emif_prio_class_serv_map; u32 emif_connect_id_serv_1_map; u32 emif_connect_id_serv_2_map; - u32 padding8[5]; + u32 padding8; + u32 emif_ecc_ctrl_reg; + u32 emif_ecc_address_range_1; + u32 emif_ecc_address_range_2; + u32 padding8_1; u32 emif_rd_wr_exec_thresh; u32 emif_cos_config; +#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE) + u32 padding9[2]; + u32 emif_1b_ecc_err_cnt; + u32 emif_1b_ecc_err_thrush; + u32 emif_1b_ecc_err_dist_1; + u32 emif_1b_ecc_err_addr_log; + u32 emif_2b_ecc_err_addr_log; + u32 emif_ddr_phy_status[28]; + u32 padding10[19]; +#else u32 padding9[6]; u32 emif_ddr_phy_status[28]; u32 padding10[20]; +#endif u32 emif_ddr_ext_phy_ctrl_1; u32 emif_ddr_ext_phy_ctrl_1_shdw; u32 emif_ddr_ext_phy_ctrl_2; diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index def7fe0f0a..2b03dbecf4 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -255,7 +255,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; u32 reg, i, phy;
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6]; phy = readl(&emif->emif_ddr_phy_ctrl_1);
/* Update PHY_REG_RDDQS_RATIO */ @@ -269,7 +269,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11]; if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { reg = readl(emif_phy_status++); @@ -279,7 +279,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16]; if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { reg = readl(emif_phy_status++);