On 10/31/07, Clemens Koller clemens.koller@anagramm.de wrote:
robert lazarski schrieb:
I've been looking at the tsec driver and the code for the 88E1111S in particular and its unclear to me so far how to ensure that all my TSEC's are in rgmii mode. Any ideas?
Just for example: Datasheet of MV88E1111, Page 48, Chapter 2.2.1: The (MAC) interface is selected by setting the HWCFG_MODE[3..0]='xxxx'.......
In the rgmii mode case we were able to verify that once the u-boot tsec code runs, it places the pordevsr register of the 8548 into rgmii - which the hardware guys tells me is all we need. We still can't ping though, nor see any arp activity on the pinged host. To reiterate:
1) We see our phy with 'mii info' :
=> mii info 0x2 PHY_PHYIDR2 @ 0x2 = 0x0cc2 PHY_PHYIDR[1,2] @ 0x2 = 0x01410cc2 PHY 0x02: OUI = 0x5043, Model = 0x0C, Rev = 0x02, 10baseT, HDX
2) We can change our 8E1111 phy via 'mii write' which tells us the mdio lines and clock are working. Here's going from the default state after hw reset to loopback mode:
=> mii dump 0x2 0 0. (1140) -- PHY control register -- (8000:0000) 0.15 = 0 reset (4000:0000) 0.14 = 0 loopback (2040:0040) 0. 6,13 = b10 speed selection = 1000 Mbps (1000:1000) 0.12 = 1 A/N enable (0800:0000) 0.11 = 0 power-down (0400:0000) 0.10 = 0 isolate (0200:0000) 0. 9 = 0 restart A/N (0100:0100) 0. 8 = 1 duplex = full (0080:0000) 0. 7 = 0 collision test enable (003f:0000) 0. 5- 0 = 0 (reserved)
=> mii write 0x2 0 0x5140 => mii dump 0x2 0 0. (5140) -- PHY control register -- (8000:0000) 0.15 = 0 reset (4000:4000) 0.14 = 1 loopback (2040:0040) 0. 6,13 = b10 speed selection = 1000 Mbps (1000:1000) 0.12 = 1 A/N enable (0800:0000) 0.11 = 0 power-down (0400:0000) 0.10 = 0 isolate (0200:0000) 0. 9 = 0 restart A/N (0100:0100) 0. 8 = 1 duplex = full (0080:0000) 0. 7 = 0 collision test enable (003f:0000) 0. 5- 0 = 0 (reserved)
Incidently, this brings the link down so we are still determining the best way to use loopback to identify the problem.
3) We can't auto negotiate. However, we can change the data speed from 1000/100/10 and see the proper signals and frequencies from the processor to the phy.
4) Our problem is we can't see any activity from the phy to the RJ45, nor succeed with pings and arp.
There was an offer a few threads back to look at our schematic. Here's the link:
http://braziloutsource.com/random/atum_85xx_ethernet.pdf
Thanks all for the continuing help, Robert