Let's make the indentation of pre-processor macros and conditionals in serial_sh.h consistent before we add to the confusion with a new SoC.
Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com --- drivers/serial/serial_sh.h | 84 +++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 149ec1fe7397..3109c5a946b9 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -116,9 +116,9 @@ struct uart_port { defined(CONFIG_CPU_SH7751R) || \ defined(CONFIG_CPU_SH7763) || \ defined(CONFIG_CPU_SH7780) -#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ +# define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ #else -#define SCI_CTRL_FLAGS_REIE 0 +# define SCI_CTRL_FLAGS_REIE 0 #endif /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ @@ -174,7 +174,7 @@ struct uart_port { #endif
#ifndef SCIF_ORER -#define SCIF_ORER 0x0000 +# define SCIF_ORER 0x0000 #endif
#define SCxSR_TEND(port)\ @@ -282,45 +282,45 @@ static inline void sci_##name##_out(struct uart_port *port,\ }
#if defined(CONFIG_R8A7740) -#if defined(CONFIG_CPU_SH7721) || \ +# if defined(CONFIG_CPU_SH7721) || \ defined(CONFIG_SH73A0) -#define SCIF_FNS(name, scif_offset, scif_size) \ +# define SCIF_FNS(name, scif_offset, scif_size) \ CPU_SCIF_FNS(name, scif_offset, scif_size) -#elif defined(CONFIG_R8A7740) -#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ +# elif defined(CONFIG_R8A7740) +# define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ sh4_scifb_offset, sh4_scifb_size) \ CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ sh4_scifb_offset, sh4_scifb_size) -#define SCIF_FNS(name, scif_offset, scif_size) \ +# define SCIF_FNS(name, scif_offset, scif_size) \ CPU_SCIF_FNS(name, scif_offset, scif_size) -#else -#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ +# else +# define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ sh4_sci_offset, sh4_sci_size, \ sh3_scif_offset, sh3_scif_size,\ sh4_scif_offset, sh4_scif_size, \ h8_sci_offset, h8_sci_size) \ CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ sh3_scif_offset, sh3_scif_size) -#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ +# define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ sh4_scif_offset, sh4_scif_size) \ CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) -#endif +# endif #elif defined(CONFIG_CPU_SH7723) - #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ - sh4_scif_offset, sh4_scif_size) \ - CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ - sh4_scif_offset, sh4_scif_size) - #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ - CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) +# define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ + sh4_scif_offset, sh4_scif_size) \ + CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ + sh4_scif_offset, sh4_scif_size) +# define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ + CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #else -#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ +# define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ sh4_sci_offset, sh4_sci_size, \ sh3_scif_offset, sh3_scif_size,\ sh4_scif_offset, sh4_scif_size, \ h8_sci_offset, h8_sci_size) \ CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ sh4_scif_offset, sh4_scif_size) -#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ +# define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ sh4_scif_offset, sh4_scif_size) \ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #endif @@ -382,11 +382,11 @@ SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) SCIF_FNS(DL, 0, 0, 0x30, 16) SCIF_FNS(CKS, 0, 0, 0x34, 16) SCIF_FNS(HSSRR, 0, 0, 0x40, 16) /* HSCIF only */ -#if defined(CFG_SCIF_A) +# if defined(CFG_SCIF_A) SCIF_FNS(SCLSR, 0, 0, 0x14, 16) -#else +# else SCIF_FNS(SCLSR, 0, 0, 0x24, 16) -#endif +# endif #else /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ /* name off sz off sz off sz off sz off sz*/ @@ -397,13 +397,13 @@ SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) -#if defined(CONFIG_CPU_SH7780) +# if defined(CONFIG_CPU_SH7780) SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) SCIF_FNS(SCLSR, 0, 0, 0x28, 16) -#elif defined(CONFIG_CPU_SH7763) +# elif defined(CONFIG_CPU_SH7763) SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) @@ -411,16 +411,16 @@ SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) SCIF_FNS(SCLSR, 0, 0, 0x28, 16) -#else +# else
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) -#if defined(CONFIG_CPU_SH7722) +# if defined(CONFIG_CPU_SH7722) SCIF_FNS(SCSPTR, 0, 0, 0, 0) -#else +# else SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) -#endif +# endif SCIF_FNS(SCLSR, 0, 0, 0x24, 16) -#endif +# endif SCIF_FNS(DL, 0, 0, 0x30, 16) SCIF_FNS(CKS, 0, 0, 0x34, 16) SCIF_FNS(HSSRR, 0, 0, 0x40, 16) /* HSCIF only */ @@ -479,10 +479,10 @@ static inline int sci_rxd_in(struct uart_port *port) */
#if defined(CONFIG_CPU_SH7780) -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) +# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #elif defined(CONFIG_CPU_SH7721) || \ defined(CONFIG_R8A7740) -#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(CONFIG_CPU_SH7723) static inline int scbrr_calc(struct uart_port *port, int bps, int clk) { @@ -491,14 +491,14 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) else return ((clk*2)+16*bps)/(16*bps)-1; } -#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) +# define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) #elif defined(CONFIG_RCAR_GEN2) -#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ - #if defined(CFG_SCIF_A) || defined(CFG_HSCIF) - #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ - #else - #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ - #endif +# define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ +# if defined(CFG_SCIF_A) || defined(CFG_HSCIF) +# define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ +# else +# define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ +# endif #elif defined(CONFIG_RCAR_64) static inline int scbrr_calc(struct uart_port *port, int bps, int clk) { @@ -507,11 +507,11 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) else /* PORT_HSCIF */ return clk / bps / 8 / 2 - 1; /* Internal Clock, Sampling rate = 8 */ } -#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) +# define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) #else /* Generic SH */ -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif
#ifndef DL_VALUE -#define DL_VALUE(bps, clk) 0 +# define DL_VALUE(bps, clk) 0 #endif