diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1333MHz.dtsi b/arch/arm/dts/k3-am654-base-board-ddr4-1333MHz.dtsi new file mode 100644 index 0000000000..c07e6519e5 --- /dev/null +++ b/arch/arm/dts/k3-am654-base-board-ddr4-1333MHz.dtsi
There is a nice EMIF tool[1] that HW team created to auto generate this data. Also they have provided 1600MHz DDR configuration for AM654. Will Repost the series with the auto generated data.
[1] http://www.ti.com/lit/pdf/spracj0
Thanks and regards, Lokesh
@@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
- */
+#define DDRCTL_DFIMISC 0x00000000 +#define DDRCTL_DFITMG0 0x04878206 +#define DDRCTL_DFITMG1 0x00060606 +#define DDRCTL_DFITMG2 0x00000504 +#define DDRCTL_INIT0 0x400100A3 +#define DDRCTL_INIT1 0x00420000 +#define DDRCTL_INIT2 0x00000000 +#define DDRCTL_INIT3 0x00100501 +#define DDRCTL_INIT4 0x00000020 +#define DDRCTL_INIT5 0x00100000 +#define DDRCTL_INIT6 0x00000480 +#define DDRCTL_INIT7 0x00000097 +#define DDRCTL_MSTR 0x41040010 +#define DDRCTL_ODTCFG 0x06000608 +#define DDRCTL_ODTMAP 0x00000001 +#define DDRCTL_RANKCTL 0x00000000 +#define DDRCTL_RFSHCTL0 0x00210070 +#define DDRCTL_RFSHCTL3 0x00000000 +#define DDRCTL_RFSHTMG 0x00510075 +#define DDRCTL_STAT 0x00000000 +#define DDRCTL_SWCTL 0x00000000 +#define DDRCTL_SWSTAT 0x00000000 +#define DDRCTL_ZQCTL0 0x21000040 +#define DDRCTL_ZQCTL1 0x00027bc8 +#define DDRCTL_CRCPARCTL0 0x1A000000 +#define DDRCTL_CRCPARCTL1 0x0048051E +#define DDRCTL_ECCCFG0 0x00000000 +#define DDRCTL_ADDRMAP0 0x001F1F1F +#define DDRCTL_ADDRMAP1 0x003f0808 +#define DDRCTL_ADDRMAP2 0x00000000 +#define DDRCTL_ADDRMAP3 0x00000000 +#define DDRCTL_ADDRMAP4 0x00001f1f +#define DDRCTL_ADDRMAP5 0x08080808 +#define DDRCTL_ADDRMAP6 0x08080808 +#define DDRCTL_ADDRMAP7 0x00000f0f +#define DDRCTL_ADDRMAP8 0x00000a0a +#define DDRCTL_ADDRMAP9 0x0000000 +#define DDRCTL_ADDRMAP10 0x0000000 +#define DDRCTL_ADDRMAP11 0x001f1f00 +#define DDRCTL_DQMAP0 0x00000000 +#define DDRCTL_DQMAP1 0x00000000 +#define DDRCTL_DQMAP4 0x00000000 +#define DDRCTL_DQMAP5 0x00000000 +#define DDRCTL_PWRCTL 0x00000000 +#define DDRCTL_DRAMTMG0 0x0b0a160b +#define DDRCTL_DRAMTMG1 0x00020310 +#define DDRCTL_DRAMTMG2 0x0506040a +#define DDRCTL_DRAMTMG3 0x0000400C +#define DDRCTL_DRAMTMG4 0x05020205 +#define DDRCTL_DRAMTMG5 0x04040302 +#define DDRCTL_DRAMTMG6 0x0000000 +#define DDRCTL_DRAMTMG7 0x00000000 +#define DDRCTL_DRAMTMG8 0x02020C04 +#define DDRCTL_DRAMTMG9 0x00020208 +#define DDRCTL_DRAMTMG11 0x1005010E +#define DDRCTL_DRAMTMG12 0x00000008 +#define DDRCTL_DRAMTMG13 0x00000000 +#define DDRCTL_DRAMTMG14 0x00000000 +#define DDRCTL_DRAMTMG15 0x00000035 +#define DDRCTL_DRAMTMG17 0x00000000 +#define DDRPHY_DCR 0x0000040C +#define DDRPHY_DSGCR 0x02A0C129 +#define DDRPHY_DX0GCR0 0x00000000 +#define DDRPHY_DX0GCR1 0x00000000 +#define DDRPHY_DX0GCR2 0x00000000 +#define DDRPHY_DX0GCR3 0x00000000 +#define DDRPHY_DX0GCR4 0x0E00c93C +#define DDRPHY_DX0GCR5 0x00000049 +#define DDRPHY_DX0GSR0 0x00000000 +#define DDRPHY_DX0GSR1 0x00000000 +#define DDRPHY_DX0GSR2 0x00000000 +#define DDRPHY_DX0GSR3 0x00000000 +#define DDRPHY_DX0GSR4 0x00000000 +#define DDRPHY_DX0GSR5 0x00000000 +#define DDRPHY_DX0GSR6 0x00000000 +#define DDRPHY_DX0GTR0 0x00020002 +#define DDRPHY_DX1GCR0 0x00000000 +#define DDRPHY_DX1GCR1 0x00000000 +#define DDRPHY_DX1GCR2 0x00000000 +#define DDRPHY_DX1GCR3 0x00000000 +#define DDRPHY_DX1GCR4 0x0E00c93C +#define DDRPHY_DX1GCR5 0x00000049 +#define DDRPHY_DX1GSR0 0x00000000 +#define DDRPHY_DX1GSR1 0x00000000 +#define DDRPHY_DX1GSR2 0x00000000 +#define DDRPHY_DX1GSR3 0x00000000 +#define DDRPHY_DX1GSR4 0x00000000 +#define DDRPHY_DX1GSR5 0x00000000 +#define DDRPHY_DX1GSR6 0x00000000 +#define DDRPHY_DX1GTR0 0x00020002 +#define DDRPHY_DX2GCR0 0x00000000 +#define DDRPHY_DX2GCR1 0x00000000 +#define DDRPHY_DX2GCR2 0x00000000 +#define DDRPHY_DX2GCR3 0x00000000 +#define DDRPHY_DX2GCR4 0x0E00c93C +#define DDRPHY_DX2GCR5 0x00000049 +#define DDRPHY_DX2GSR0 0x00000000 +#define DDRPHY_DX2GSR1 0x00000000 +#define DDRPHY_DX2GSR2 0x00000000 +#define DDRPHY_DX2GSR3 0x00000000 +#define DDRPHY_DX2GSR4 0x00000000 +#define DDRPHY_DX2GSR5 0x00000000 +#define DDRPHY_DX2GSR6 0x00000000 +#define DDRPHY_DX2GTR0 0x00020002 +#define DDRPHY_DX3GCR0 0x00000000 +#define DDRPHY_DX3GCR1 0x00000000 +#define DDRPHY_DX3GCR2 0x00000000 +#define DDRPHY_DX3GCR3 0x00000000 +#define DDRPHY_DX3GCR4 0x0E00c93C +#define DDRPHY_DX3GCR5 0x00000049 +#define DDRPHY_DX3GSR0 0x00000000 +#define DDRPHY_DX3GSR1 0x00000000 +#define DDRPHY_DX3GSR2 0x00000000 +#define DDRPHY_DX3GSR3 0x00000000 +#define DDRPHY_DX3GSR4 0x00000000 +#define DDRPHY_DX3GSR5 0x00000000 +#define DDRPHY_DX3GSR6 0x00000000 +#define DDRPHY_DX3GTR0 0x00020002 +#define DDRPHY_DX4GCR0 0x40703260 +#define DDRPHY_DX4GCR1 0x55556000 +#define DDRPHY_DX4GCR2 0xaaaa0000 +#define DDRPHY_DX4GCR3 0xffe18587 +#define DDRPHY_DX4GCR4 0x00000000 +#define DDRPHY_DX4GCR5 0x00000000 +#define DDRPHY_DX4GSR0 0x00000000 +#define DDRPHY_DX4GSR1 0x00000000 +#define DDRPHY_DX4GSR2 0x00000000 +#define DDRPHY_DX4GSR3 0x00000000 +#define DDRPHY_DX4GSR4 0x00000000 +#define DDRPHY_DX4GSR5 0x00000000 +#define DDRPHY_DX4GSR6 0x00000000 +#define DDRPHY_DX4GTR0 0x00000000 +#define DDRPHY_DX8SL0DQSCTL 0x00000000 +#define DDRPHY_DX8SL0DXCTL2 0x00141830 +#define DDRPHY_DX8SL0IOCR 0x04800000 +#define DDRPHY_DX8SL0PLLCR0 0x021c4000 +#define DDRPHY_DX8SL1DQSCTL 0x00000000 +#define DDRPHY_DX8SL1DXCTL2 0x00141830 +#define DDRPHY_DX8SL1IOCR 0x04800000 +#define DDRPHY_DX8SL1PLLCR0 0x021c4000 +#define DDRPHY_DX8SL2DQSCTL 0x00000000 +#define DDRPHY_DX8SL2DXCTL2 0x00141830 +#define DDRPHY_DX8SL2IOCR 0x04800000 +#define DDRPHY_DX8SL2PLLCR0 0x021c4000 +#define DDRPHY_DXCCR 0x00000038 +#define DDRPHY_ODTCR 0x00010000 +#define DDRPHY_PGCR0 0x00000000 +#define DDRPHY_PGCR1 0x020046C0 +#define DDRPHY_PGCR2 0x00F09f60 +#define DDRPHY_PGCR3 0x55AA0080 +#define DDRPHY_PGCR5 0x01010004 +#define DDRPHY_PGCR6 0x00013001 +#define DDRPHY_PGSR0 0x00000000 +#define DDRPHY_DTCR0 0x8000B1c7 +#define DDRPHY_DTCR1 0x00010236 +#define DDRPHY_MR0 0x00000010 +#define DDRPHY_MR1 0x00000501 +#define DDRPHY_MR2 0x00000000 +#define DDRPHY_MR3 0x00000020 +#define DDRPHY_MR4 0x00000000 +#define DDRPHY_MR5 0x00000480 +#define DDRPHY_MR6 0x00000097 +#define DDRPHY_MR11 0x00000000 +#define DDRPHY_MR12 0x00000000 +#define DDRPHY_MR13 0x00000000 +#define DDRPHY_MR14 0x00000000 +#define DDRPHY_MR22 0x00000000 +#define DDRPHY_PIR 0x00000000 +#define DDRPHY_PLLCR0 0x021c4000 +#define DDRPHY_RANKIDR 0x0000000 +#define DDRPHY_VTCR0 0xF3C32017 +#define DDRPHY_ACIOCR5 0x04800000 +#define DDRPHY_IOVCR0 0x0F0C0C0C +#define DDRPHY_DTPR0 0x04160905 +#define DDRPHY_DTPR1 0x28140000 +#define DDRPHY_DTPR2 0x00040300 +#define DDRPHY_DTPR3 0x02800000 +#define DDRPHY_DTPR4 0x00ea0704 +#define DDRPHY_DTPR5 0x001f0905 +#define DDRPHY_DTPR6 0x00000505 +#define DDRPHY_PTR2 0x00000000 +#define DDRPHY_PTR3 0x00061A80 +#define DDRPHY_PTR4 0x000000E0 +#define DDRPHY_PTR5 0x00027100 +#define DDRPHY_PTR6 0x04000320 +#define DDRPHY_ZQCR 0x008A2A58 +#define DDRPHY_ZQ0PR0 0x000077DD +#define DDRPHY_ZQ1PR0 0x000077DD +#define DDRPHY_ZQ2PR0 0x000077DD +#define DDRPHY_ZQ3PR0 0x000077DD