Dear Prafulla Wadaskar,
In message 1238798370-9245-1-git-send-email-prafulla@marvell.com you wrote:
This is ARM v5TE-compliant processor core with MMU and L1/L2 Cache
Signed-off-by: prafulla_wadaskar prafulla@marvell.com Reviewed by: Ronen Shitrit rshitrit@marvell.com
cpu/arm926ejs/start.S | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index ed4932a..08ec955 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -214,10 +214,15 @@ cpu_init_crit: * disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 +#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131)
- bic r0, r0, #0x00000007 /* clear bits 2:0 (CAM) */
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
+#else bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ +#endif mcr p15, 0, r0, c1, c0, 0
Why is this special case needed?
Cannot you enable the IC, too?
Best regards,
Wolfgang Denk