Assuming the OSes exception vectors start from the base of kernel address, and the kernel physical starting address can be relocated to an non-zero address. This patch enables the second core to have a valid IVPR for debugger before kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid value for second core which runs kernel at different physical address other than 0x0.
Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- cpu/mpc85xx/release.S | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 7c3e8a1..d35e4ee 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -157,6 +157,7 @@ __secondary_start_page: mfspr r0,SPRN_PIR stw r0,ENTRY_PIR(r10)
+ mtspr IVPR,r12 /* * Coming here, we know the cpu has one TLB mapping in TLB1[0] * which maps 0xfffff000-0xffffffff one-to-one. We set up a