Re: [U-Boot] [PATCH 2/2] ARM: add SBx81LIFKW board

Hi Chris,

On 28.05.2018 11:00, Chris Packham wrote:

This is a series of line cards for Allied Telesis's SBx8100 chassis switch. The CPU block is common to the SBx81GS24a, SBx81XS6, SBx81XS16 and SBx81GT40 cards collectively referred to as SBx81LIFKW in u-boot.

Signed-off-by: Chris Packham judge.packham@gmail.com

This is the board I've been using for testing the device tree support for kirkwood. The Ethernet arrangement is a bit complicated and doesn't currently work on u-boot#master but I can test SPI and I2C.

arch/arm/dts/kirkwood-atl-sbx81lifkw.dts | 133 ++++++++++++++ arch/arm/mach-kirkwood/Kconfig | 4 + board/alliedtelesis/SBx81LIFKW/Kconfig | 12 ++ board/alliedtelesis/SBx81LIFKW/MAINTAINERS | 7 + board/alliedtelesis/SBx81LIFKW/Makefile | 8 + board/alliedtelesis/SBx81LIFKW/kwbimage.cfg | 47 +++++ board/alliedtelesis/SBx81LIFKW/platform.S | 108 +++++++++++ board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 192 ++++++++++++++++++++ configs/SBx81LIFKW_defconfig | 32 ++++ include/configs/SBx81LIFKW.h | 123 +++++++++++++ 10 files changed, 666 insertions(+) create mode 100644 arch/arm/dts/kirkwood-atl-sbx81lifkw.dts create mode 100644 board/alliedtelesis/SBx81LIFKW/Kconfig create mode 100644 board/alliedtelesis/SBx81LIFKW/MAINTAINERS create mode 100644 board/alliedtelesis/SBx81LIFKW/Makefile create mode 100644 board/alliedtelesis/SBx81LIFKW/kwbimage.cfg create mode 100644 board/alliedtelesis/SBx81LIFKW/platform.S create mode 100644 board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c create mode 100644 configs/SBx81LIFKW_defconfig create mode 100644 include/configs/SBx81LIFKW.h

diff --git a/arch/arm/dts/kirkwood-atl-sbx81lifkw.dts b/arch/arm/dts/kirkwood-atl-sbx81lifkw.dts new file mode 100644 index 000000000000..e5b1efa1415a --- /dev/null +++ b/arch/arm/dts/kirkwood-atl-sbx81lifkw.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/;

+#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi"

+/ {

• model = "Allied Telesis SBx81LIFKW Board";
• compatible = "atl,SBx81LIFKW", "marvell,kirkwood-88f6281",

•      "marvell,kirkwood";
  

• memory {

• device_type = "memory";
  

• reg = <0x00000000 0x08000000>; /* 128 MB */
  

• };
• chosen {

• bootargs = "console=ttyS0,115200n8 earlyprintk";
  

• stdout-path = &uart0;
  

• };
• aliases {

• ethernet0 = &eth0;
  

• i2c0 = &i2c0;
  

• spi0 = &spi0;
  

• };
• dsa {

• compatible = "marvell,dsa";
  

• #address-cells = <2>;
  

• #size-cells = <0>;
  

• dsa,ethernet = <&eth0>;
  

• dsa,mii-bus = <&mdio>;
  

• status = "okay";
  

• switch@0 {
  

• 	#address-cells =  <1>;
  

• 	#size-cells = <0>;
  

• 	reg = <1 0>;
  

• 	port@0 {
  

• 		reg = <0>;
  

• 		label = "internal0";
  

• 	};
  

• 	port@1 {
  

• 		reg = <1>;
  

• 		label = "internal1";
  

• 	};
  

• 	port@8 {
  

• 		reg = <8>;
  

• 		label = "internal8";
  

• 		phy-mode = "rgmii-id";
  

• 		fixed-link {
  

• 			speed = <1000>;
  

• 			full-duplex;
  

• 		};
  

• 	};
  

• 	port@9 {
  

• 		reg = <9>;
  

• 		label = "internal9";
  

• 		phy-mode = "rgmii-id";
  

• 		fixed-link {
  

• 			speed = <1000>;
  

• 			full-duplex;
  

• 		};
  

• 	};
  

• 	port@10 {
  

• 		reg = <10>;
  

• 		label = "cpu";
  

• 	};
  

• };
  

• };

+};

+&spi0 {

• status = "okay";
• flash@0 {

• #address-cells = <1>;
  

• #size-cells = <1>;
  

• compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
  

• reg = <0>;
  

• spi-max-frequency = <50000000>;
  

• mode = <0>;
  

• partition@u-boot {
  

• 	reg = <0x00000000 0x00c00000>;
  

• 	label = "u-boot";
  

• };
  

• partition@u-boot-env {
  

• 	reg = <0x00c00000 0x00040000>;
  

• 	label = "u-boot-env";
  

• };
  

• partition@unused {
  

• 	reg = <0x00100000 0x00f00000>;
  

• 	label = "unused";
  

• };
  

• };

+};

+&i2c0 {

• status = "okay";
• eeprom@52 {

• compatible = "atmel,24c04";
  

• reg = <0x52>;
  

• };

+};

+&uart0 {

• status = "okay";

+};

+&mdio {

• status = "okay";

+};

+&eth0 {

• status = "okay";
• ethernet0-port@0 {

• speed = <1000>;
  

• duplex = <1>;
  

• };

+};

+&pciec {

• status = "okay";

+};

+&pcie0 {

• status = "okay";

+}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 2dd107a8b3bf..5a5a63cea719 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -59,6 +59,9 @@ config TARGET_NAS220 config TARGET_NSA310S bool "Zyxel NSA310S"

+config TARGET_SBx81LIFKW

• bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"

• endchoice

  config SYS_SOC

@@ -81,5 +84,6 @@ source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" source "board/Seagate/nas220/Kconfig" source "board/zyxel/nsa310s/Kconfig" +source "board/alliedtelesis/SBx81LIFKW/Kconfig"

endif diff --git a/board/alliedtelesis/SBx81LIFKW/Kconfig b/board/alliedtelesis/SBx81LIFKW/Kconfig new file mode 100644 index 000000000000..5c2609b7f464 --- /dev/null +++ b/board/alliedtelesis/SBx81LIFKW/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SBx81LIFKW

+config SYS_BOARD

•   default "SBx81LIFKW"
  

+config SYS_VENDOR

•   default "alliedtelesis"
  

+config SYS_CONFIG_NAME

•   default "SBx81LIFKW"
  

+endif diff --git a/board/alliedtelesis/SBx81LIFKW/MAINTAINERS b/board/alliedtelesis/SBx81LIFKW/MAINTAINERS new file mode 100644 index 000000000000..31ccec0e9b7e --- /dev/null +++ b/board/alliedtelesis/SBx81LIFKW/MAINTAINERS @@ -0,0 +1,7 @@ +SBx81LIFKW BOARD +M: Chris Packham chris.packham@alliedtelesis.co.nz +S: Maintained +F: board/alliedtelesis/SBx81LIFKW/ +F: include/configs/SBx81LIFKW +F: configs/SBx81LIFKW_defconfig +F: arch/arm/dts/kirkwood-atl-sbx81lifkw.dts diff --git a/board/alliedtelesis/SBx81LIFKW/Makefile b/board/alliedtelesis/SBx81LIFKW/Makefile new file mode 100644 index 000000000000..2a5a33fa0807 --- /dev/null +++ b/board/alliedtelesis/SBx81LIFKW/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010, 2018 +# Allied Telesis <www.alliedtelesis.com> +#

+obj-y += sbx81lifkw.o +obj-y += platform.o diff --git a/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg b/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg new file mode 100644 index 000000000000..9726f15e28b0 --- /dev/null +++ b/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2018 Allied Telesis +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +#

+# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash

+# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed +DATA 0xffd100e0 0x1b1b1b1b +DATA 0xffd20134 0xffffffff +DATA 0xffd20138 0x009fffff +DATA 0xffd20154 0x00000000 +DATA 0xffd2014c 0x00000000 +DATA 0xffd20148 0x00000001

+# Dram initalization for 1 x x16 +# DDR II Micron part number MT47H64M16HR-3 +# MClk 333MHz, Size 128MB, ECC disable +# +DATA 0xffd01400 0x43000618 +DATA 0xffd01404 0x35143000 +DATA 0xffd01408 0x11012227 +DATA 0xffd0140c 0x00000819 +DATA 0xffd01410 0x0000000d +DATA 0xffd01414 0x00000000 +DATA 0xffd01418 0x00000000 +DATA 0xffd0141c 0x00000632 +DATA 0xffd01420 0x00000040 +DATA 0xffd01424 0x0000f07f +DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000 +DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB +DATA 0xffd01508 0x10000000 +DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled +DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled +DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled +DATA 0xffd01494 0x00030000 +DATA 0xffd01498 0x00000000 +DATA 0xffd0149c 0x0000e803 +DATA 0xffd01480 0x00000001

+# End of Header extension +DATA 0x0 0x0 diff --git a/board/alliedtelesis/SBx81LIFKW/platform.S b/board/alliedtelesis/SBx81LIFKW/platform.S new file mode 100644 index 000000000000..44ce603696af --- /dev/null +++ b/board/alliedtelesis/SBx81LIFKW/platform.S @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • (C) Copyright 2010
• • Allied Telesis <www.alliedtelesis.com>
• */

+/* based (loosley) on Marvell's board/mv_feroceon/mv_kw/platform.S */

+#include <config.h>

+platform_lowlevel_init_data:

• /* AHB to Mbus Bridge

• * Change CPU reg base to 0xF1000000
  

• *  These *MUST* be first, and it hits
  

• *  both potential address to be safe
  

• */
  

• .long 0xD0020080, KW_REGS_PHY_BASE
• .long 0xF1020080, KW_REGS_PHY_BASE
• /* Configure RGMII-0 interface pad voltage to 1.8V */
• .long KW_REGS_PHY_BASE + 0x100E0, 0x1B1B1B1B
• .long KW_REGS_PHY_BASE + 0x20134, 0xffffffff
• .long KW_REGS_PHY_BASE + 0x20138, 0x009fffff
• .long KW_REGS_PHY_BASE + 0x20154, 0x00000000
• .long KW_REGS_PHY_BASE + 0x2014c, 0x00000000
• .long KW_REGS_PHY_BASE + 0x20148, 0x00000001
• /* Dram initalization for 1 x x16

• *  DDR II Micron part number MT47H64M16HR-3
  

• *  MClk 333MHz, Size 128MB, ECC disable
  

• */
  

• .long KW_REGS_PHY_BASE + 0x01400, 0x43000618 /* DDR Configuration register */
• .long KW_REGS_PHY_BASE + 0x01404, 0x35143000 /* DDR Controller Control Low */
• .long KW_REGS_PHY_BASE + 0x01408, 0x11012227 /* DDR Timing (Low) (active cycles value +1) */
• .long KW_REGS_PHY_BASE + 0x0140C, 0x00000819 /* DDR Timing (High) */
• .long KW_REGS_PHY_BASE + 0x01410, 0x0000000d /* DDR Address Control */
• .long KW_REGS_PHY_BASE + 0x01414, 0x00000000 /* DDR Open Pages Control */
• .long KW_REGS_PHY_BASE + 0x01418, 0x00000000 /* DDR Operation */
• .long KW_REGS_PHY_BASE + 0x0141C, 0x00000632 /* DDR Mode */
• .long KW_REGS_PHY_BASE + 0x01420, 0x00000040 /* DDR Extended Mode */
• .long KW_REGS_PHY_BASE + 0x01424, 0x0000f07f /* DDR Controller Control High */
• .long KW_REGS_PHY_BASE + 0x01428, 0x00063300 /* DDR2 ODT Read Timing (default values) */
• .long KW_REGS_PHY_BASE + 0x0147C, 0x00006330 /* DDR2 ODT Write Timing (default values) */
• .long KW_REGS_PHY_BASE + 0x01500, 0x00000000 /* SDRAM CS[0] Base address at 0x00000000 */
• .long KW_REGS_PHY_BASE + 0x01504, 0x07FFFFF1 /* SDRAM CS[0] Size 128MiB */
• .long KW_REGS_PHY_BASE + 0x01508, 0x10000000 /* SDRAM CS[1] Base address */
• .long KW_REGS_PHY_BASE + 0x0150C, 0x00FFFFF4 /* SDRAM CS[1] Size, window disabled */
• .long KW_REGS_PHY_BASE + 0x01510, 0x20000000 /* SDRAM CS[2] Base address */
• .long KW_REGS_PHY_BASE + 0x01514, 0x00FFFFF8 /* SDRAM CS[2] Size, window disabled */
• .long KW_REGS_PHY_BASE + 0x01518, 0x30000000 /* SDRAM CS[3] Base address */
• .long KW_REGS_PHY_BASE + 0x0151C, 0x00FFFFFC /* SDRAM CS[3] Size, window disabled */
• .long KW_REGS_PHY_BASE + 0x01494, 0x00030000 /* DDR ODT Control (Low) */
• .long KW_REGS_PHY_BASE + 0x01498, 0x00000000 /* DDR ODT Control (High) */
• .long KW_REGS_PHY_BASE + 0x0149C, 0x0000e803 /* CPU ODT Control */
• .long KW_REGS_PHY_BASE + 0x01480, 0x00000001 /* DDR Initialization Control */
• /* End of Header extension */
• .long 0x0, 0x0

My experience with Kirkwood and its code base is limited. But why do you have this DDR setup again in this .S file? Its already done in the SPI NOR header "kwbimage.cfg".

This is just a first comment - I'll do a more thorough review later.

Thanks, Stefan