Re: [U-Boot] [PATCH v3] ppc4xx: Add GDsys CompactCenter board support.

Hi, Dirk

The bootstrap.c file is the same as for Canyonlands. Maybe it makes sense to share it between all 460EX boards, by moving it to some common location. Stefan, what do you think ?

Felix.

Dirk Eibach wrote:

Board support for the Guntermann & Drunck CompactCenter and DevCon-Center. Based on the AMCC Canyonlands board support by Stefan Roese.

Signed-off-by: Dirk Eibach eibach@gdsys.de

Changes since v1:

• removed dead code
• whitespace cleanup
• simplified code for nand/nor distinction in board/gdsys/compactcenter/bootstrap.c

Changes since v2:

• removed get_cpu_num() from board/gdsys/compactcenter/compactcenter.c
• use __ft_board_setup() instead of ft_cpu_setup()
• cleanup CompactCenter/Canyonlands mixup
• reformatted CONFIG_SYS_4xx_GPIO_TABLE. Lines are > 80 chars but readable.

MAINTAINERS | 2 + MAKEALL | 2 + Makefile | 8 + board/gdsys/compactcenter/Makefile | 52 ++++ board/gdsys/compactcenter/bootstrap.c | 164 +++++++++++ board/gdsys/compactcenter/compactcenter.c | 328 ++++++++++++++++++++++ board/gdsys/compactcenter/config.mk | 41 +++ board/gdsys/compactcenter/init.S | 97 +++++++ board/gdsys/compactcenter/u-boot.lds | 144 ++++++++++ include/configs/compactcenter.h | 430 +++++++++++++++++++++++++++++ 10 files changed, 1268 insertions(+), 0 deletions(-) create mode 100644 board/gdsys/compactcenter/Makefile create mode 100644 board/gdsys/compactcenter/bootstrap.c create mode 100644 board/gdsys/compactcenter/compactcenter.c create mode 100644 board/gdsys/compactcenter/config.mk create mode 100644 board/gdsys/compactcenter/init.S create mode 100644 board/gdsys/compactcenter/u-boot.lds create mode 100644 include/configs/compactcenter.h

diff --git a/MAINTAINERS b/MAINTAINERS index 0041112..ea87863 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -135,6 +135,8 @@ Jon Diekema jon.diekema@smiths-aerospace.com

Dirk Eibach eibach@gdsys.de

• compactcenter PPC460EX
• devconcenter PPC460EX gdppc440etx PPC440EP/GR neo PPC405EP

diff --git a/MAKEALL b/MAKEALL index 41f1445..84b04ce 100755 --- a/MAKEALL +++ b/MAKEALL @@ -183,6 +183,7 @@ LIST_4xx=" \ canyonlands \ canyonlands_nand \ CMS700 \

• compactcenter \ CPCI2DP \ CPCI405 \ CPCI4052 \

@@ -193,6 +194,7 @@ LIST_4xx=" \ csb272 \ csb472 \ DASA_SIM \

• devconcenter \ DP405 \ DU405 \ DU440 \

diff --git a/Makefile b/Makefile index 2a06440..5dba5a8 100644 --- a/Makefile +++ b/Makefile @@ -1299,6 +1299,14 @@ CATcenter_33_config: unconfig CMS700_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx cms700 esd

+# Compact-Center & DevCon-Center use different U-Boot images +compactcenter_config \ +devconcenter_config: unconfig

• @mkdir -p $(obj)include
• @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \

• tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
  

• @$(MKCONFIG) -n $@ -a compactcenter ppc ppc4xx compactcenter gdsys

CPCI2DP_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd

diff --git a/board/gdsys/compactcenter/Makefile b/board/gdsys/compactcenter/Makefile new file mode 100644 index 0000000..2aeead6 --- /dev/null +++ b/board/gdsys/compactcenter/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2008 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#

+include $(TOPDIR)/config.mk

+LIB = $(obj)lib$(BOARD).a

+COBJS := $(BOARD).o +COBJS += bootstrap.o +SOBJS := init.o

+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS))

+$(LIB): $(OBJS) $(SOBJS)

• $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)

+clean:

• rm -f $(SOBJS) $(OBJS)

+distclean: clean

• rm -f $(LIB) core *.bak $(obj).depend

+#########################################################################

+# defines $(obj).depend target +include $(SRCTREE)/rules.mk

+sinclude $(obj).depend

+######################################################################### diff --git a/board/gdsys/compactcenter/bootstrap.c b/board/gdsys/compactcenter/bootstrap.c new file mode 100644 index 0000000..a5be21a --- /dev/null +++ b/board/gdsys/compactcenter/bootstrap.c @@ -0,0 +1,164 @@ +/*

• • (C) Copyright 2008
• • Stefan Roese, DENX Software Engineering, sr@denx.de.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <command.h> +#include <i2c.h> +#include <asm/io.h>

+/*

• • NOR and NAND boot options change bytes 5, 6, 8, 9, 11. The
• • values are independent of the rest of the clock settings.
• */

+#define NAND_COMPATIBLE 0x01 +#define NOR_COMPATIBLE 0x02

+#define I2C_EEPROM_ADDR 0x54

+static char *config_labels[] = {

• "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
• "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
• "CPU:1000 PLB: 200 OPB: 100 EBC: 100",
• "CPU:1066 PLB: 266 OPB: 88 EBC: 88",
• NULL

+};

+static u8 boot_configs[][17] = {

• {

• (NAND_COMPATIBLE | NOR_COMPATIBLE),
  

• 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08,
  

• 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  

• },
• {

• (NAND_COMPATIBLE | NOR_COMPATIBLE),
  

• 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08,
  

• 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  

• },
• {

• (NAND_COMPATIBLE | NOR_COMPATIBLE),
  

• 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, 0x40, 0x08,
  

• 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  

• },
• {

• (NAND_COMPATIBLE | NOR_COMPATIBLE),
  

• 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, 0x40, 0x08,
  

• 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  

• },
• {

• 0,
  

• 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
  

• }

+};

+/*

• • Bytes 5,6,8,9,11 change for NAND boot
• • Values for 2k page size NAND chips
• */

+static u8 nand_boot[] = {

• 0x90, 0x01, 0xa0, 0xe8, 0x58

+};

+static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{

• u8 *buf, b_nand;
• int x, y, nbytes, selcfg;
• extern char console_buffer[];
• if (argc < 2) {

• printf("Usage:\n%s\n", cmdtp->usage);
  

• return 1;
  

• }
• if ((strcmp(argv[1], "nor") != 0) &&

•    (strcmp(argv[1], "nand") != 0)) {
  

• printf("Unsupported boot-device - only nor|nand support\n");
  

• return 1;
  

• }
• /* set the nand flag based on provided input */
• if ((strcmp(argv[1], "nand") == 0))

• b_nand = NAND_COMPATIBLE;
  

• else

• b_nand = NOR_COMPATIBLE;
  

• printf("Available configurations: \n\n");
• for (x = 0, y = 0; boot_configs[x][0] != 0; x++) {

• if (boot_configs[x][0] & b_nand) {
  

• 	printf(" %d - %s\n", (y+1), config_labels[x]);
  

• 	y++;
  

• }
  

• }
• do {

• nbytes = readline(" Selection [1-x / quit]: ");
  

• if (nbytes) {
  

• 	if (strcmp(console_buffer, "quit") == 0)
  

• 		return 0;
  

• 	selcfg = simple_strtol(console_buffer, NULL, 10);
  

• 	if ((selcfg < 1) || (selcfg > y))
  

• 		nbytes = 0;
  

• }
  

• } while (nbytes == 0);
• y = (selcfg - 1);
• for (x = 0; boot_configs[x][0] != 0; x++) {

• if (boot_configs[x][0] & b_nand) {
  

• 	if (y > 0)
  

• 		y--;
  

• 	else if (y < 1)
  

• 		break;
  

• }
  

• }
• buf = &boot_configs[x][1];
• if (b_nand) {

• buf[5] = nand_boot[0];
  

• buf[6] = nand_boot[1];
  

• buf[8] = nand_boot[2];
  

• buf[9] = nand_boot[3];
  

• buf[11] = nand_boot[4];
  

• }
• if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)

• printf("Error writing to EEPROM at address 0x%x\n",
  

• 	I2C_EEPROM_ADDR);
  

• udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
• printf("Done\n");
• printf("Please power-cycle the board for the changes to take effect\n");
• return 0;

+}

+U_BOOT_CMD(

• bootstrap, 2, 0, do_bootstrap,
• "bootstrap - program the I2C bootstrap EEPROM\n",
• "<nand|nor> - strap to boot from NAND or NOR flash\n"
• );

diff --git a/board/gdsys/compactcenter/compactcenter.c b/board/gdsys/compactcenter/compactcenter.c new file mode 100644 index 0000000..3e75180 --- /dev/null +++ b/board/gdsys/compactcenter/compactcenter.c @@ -0,0 +1,328 @@ +/*

• • (C) Copyright 2009
• • Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
• • Based on board/amcc/canyonlands/canyonlands.c
• • (C) Copyright 2008
• • Stefan Roese, DENX Software Engineering, sr@denx.de.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <ppc440.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/4xx_pcie.h> +#include <asm/gpio.h>

+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];

+DECLARE_GLOBAL_DATA_PTR;

+#define CONFIG_SYS_BCSR3_PCIE 0x10

+int board_early_init_f(void) +{

• u32 pvr = get_pvr();
• /*

• * Setup the interrupt controller polarities, triggers, etc.
  

• */
  

• mtdcr(uic0sr, 0xffffffff); /* clear all */
• mtdcr(uic0er, 0x00000000); /* disable all */
• mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
• mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
• mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
• mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
• mtdcr(uic0sr, 0xffffffff); /* clear all */
• mtdcr(uic1sr, 0xffffffff); /* clear all */
• mtdcr(uic1er, 0x00000000); /* disable all */
• mtdcr(uic1cr, 0x00000000); /* all non-critical */
• mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
• mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
• mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
• mtdcr(uic1sr, 0xffffffff); /* clear all */
• mtdcr(uic2sr, 0xffffffff); /* clear all */
• mtdcr(uic2er, 0x00000000); /* disable all */
• mtdcr(uic2cr, 0x00000000); /* all non-critical */
• mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
• mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
• mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
• mtdcr(uic2sr, 0xffffffff); /* clear all */
• mtdcr(uic3sr, 0xffffffff); /* clear all */
• mtdcr(uic3er, 0x00000000); /* disable all */
• mtdcr(uic3cr, 0x00000000); /* all non-critical */
• mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
• mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
• mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
• mtdcr(uic3sr, 0xffffffff); /* clear all */
• /*

• * Configure PFC (Pin Function Control) registers
  

• * enable GPIO 49-63
  

• * UART0: 4 pins
  

• */
  

• mtsdr(SDR0_PFC0, 0x00007fff);
• mtsdr(SDR0_PFC1, 0x00040000);
• /* Enable PCI host functionality in SDR0_PCI0 */
• mtsdr(SDR0_PCI0, 0xe0000000);
• mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
• /* Setup PLB4-AHB bridge based on the system address map */
• mtdcr(AHB_TOP, 0x8000004B);
• mtdcr(AHB_BOT, 0x8000004B);
• if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {

• /*
  

•  * Configure USB-STP pins as alternate and not GPIO
  

•  * It seems to be neccessary to configure the STP pins as GPIO
  

•  * input at powerup (perhaps while USB reset is asserted). So
  

•  * we configure those pins to their "real" function now.
  

•  */
  

• gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
  

• gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
  

• }
• /* Trigger board component reset */
• out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
• out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
• udelay(50);
• out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
• out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
• udelay(50);
• out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
• out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
• return 0;

+}

+int get_cpu_num(void) +{

• int cpu = NA_OR_UNKNOWN_CPU;
• return cpu;

+}

+int checkboard(void) +{

• char *s = getenv("serial#");

+#ifdef CONFIG_DEVCONCENTER

• printf("Board: DevCon-Center");

+#else

• printf("Board: CompactCenter");

+#endif

• if (s != NULL) {

• puts(", serial# ");
  

• puts(s);
  

• }
• putc('\n');
• return 0;

+}

+/*

• • pci_target_init
• • The bootstrap configuration provides default settings for the pci
• • inbound map (PIM). But the bootstrap config choices are limited and
• • may not be sufficient for a given board.
• */

+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{

• /*

• * Disable everything
  

• */
  

• out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
• out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
• out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
• out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
• /*

• * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
  

• * strapping options to not support sizes such as 128/256 MB.
  

• */
  

• out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
• out_le32((void *)PCIX0_PIM0LAH, 0);
• out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
• out_le32((void *)PCIX0_BAR0, 0);
• /*

• * Program the board's subsystem id/vendor id
  

• */
  

• out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
• out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
• out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);

+} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */

+#if defined(CONFIG_PCI) +/*

• • is_pci_host
• • This routine is called to determine if a pci scan should be
• • performed. With various hardware environments (especially cPCI and
• • PPMC) it's insufficient to depend on the state of the arbiter enable
• • bit in the strap register, or generic host/adapter assumptions.
• • Rather than hard-code a bad assumption in the general 440 code, the
• • 440 pci code requires the board to decide at runtime.
• • Return 0 for adapter mode, non-zero for host (monarch) mode.
• */

+int is_pci_host(struct pci_controller *hose) +{

• /* Board is always configured as host. */
• return 1;

+} +#endif /* CONFIG_PCI */

+int board_early_init_r(void) +{

• /*

• * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
  

• * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
  

• * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
  

• * To solve this problem, the FLASH has to get remapped to another
  

• * EBC address which accepts bigger regions:
  

• *
  

• * 0xfn00.0000 -> 4.cn00.0000
  

• */
  

• u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?

• EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
  

• /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
• mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L

• | bxcr_bw
  

• | EBC_BXCR_BU_RW
  

• | EBC_BXCR_BW_16BIT);
  

• /* Remove TLB entry of boot EBC mapping */
• remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
• /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
• program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,

• 	CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
  

• /*

• * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
  

• * 0xfc00.0000 is possible
  

• */
  

• /*

• * Clear potential errors resulting from auto-calibration.
  

• * If not done, then we could get an interrupt later on when
  

• * exceptions are enabled.
  

• */
  

• set_mcsr(get_mcsr());
• return 0;

+}

+int misc_init_r(void) +{

• u32 sdr0_srst1 = 0;
• u32 eth_cfg;
• u32 pvr = get_pvr();
• /*

• * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
  

• * This is board specific, so let's do it here.
  

• */
  

• mfsdr(SDR0_ETH_CFG, eth_cfg);
• /* disable SGMII mode */
• eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |

•      SDR0_ETH_CFG_SGMII1_ENABLE |
  

•      SDR0_ETH_CFG_SGMII0_ENABLE);
  

• /* Set the for 2 RGMII mode */
• /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
• eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
• if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))

• eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
  

• else

• eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
  

• mtsdr(SDR0_ETH_CFG, eth_cfg);
• /*

• * The AHB Bridge core is held in reset after power-on or reset
  

• * so enable it now
  

• */
  

• mfsdr(SDR0_SRST1, sdr0_srst1);
• sdr0_srst1 &= ~SDR0_SRST1_AHB;
• mtsdr(SDR0_SRST1, sdr0_srst1);
• return 0;

+}

+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +extern void __ft_board_setup(void *blob, bd_t *bd);

+void ft_board_setup(void *blob, bd_t *bd) +{

• int rc;
• int i;
• u32 bxcr;
• u32 ranges[EBC_NUM_BANKS * 4];
• u32 *p = ranges;
• __ft_board_setup(blob, bd);
• /* Fixup NOR mapping */
• *p++ = 0; /* chip select number */
• *p++ = 0; /* always 0 */
• *p++ = CONFIG_SYS_FLASH_BASE_PHYS_L; /* we fixed up this address */
• *p++ = gd->bd->bi_flashsize;
• for (i = 1; i < EBC_NUM_BANKS; i++) {

• mtdcr(ebccfga, EBC_BXCR(i));
  

• bxcr = mfdcr(ebccfgd);
  

• if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
  

• 	*p++ = i;
  

• 	*p++ = 0;
  

• 	*p++ = bxcr & EBC_BXCR_BAS_MASK;
  

• 	*p++ = EBC_BXCR_BANK_SIZE(bxcr);
  

• }
  

• }
• rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", ranges,

• 		  (p - ranges) * sizeof(u32), 1);
  

• if (rc) {

• printf("Unable to update property EBC mappings, err=%s\n",
  

•        fdt_strerror(rc));
  

• }
• fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",

• 	     "disabled", sizeof("disabled"), 1);
  

• fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",

• 	     "disabled", sizeof("disabled"), 1);
  

+} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/gdsys/compactcenter/config.mk b/board/gdsys/compactcenter/config.mk new file mode 100644 index 0000000..56e397d --- /dev/null +++ b/board/gdsys/compactcenter/config.mk @@ -0,0 +1,41 @@ +# +# (C) Copyright 2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# G&D CompactCenter +#

+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp

+ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif

+PLATFORM_CPPFLAGS += -DCONFIG_440=1

+ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif

+ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/gdsys/compactcenter/init.S b/board/gdsys/compactcenter/init.S new file mode 100644 index 0000000..e205c9d --- /dev/null +++ b/board/gdsys/compactcenter/init.S @@ -0,0 +1,97 @@ +/*

• • (C) Copyright 2009
• • Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
• • Based on board/amcc/canyonlands/init.S
• • (C) Copyright 2008
• • Stefan Roese, DENX Software Engineering, sr@denx.de.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <ppc_asm.tmpl> +#include <config.h> +#include <asm-ppc/mmu.h>

+/**************************************************************************

• • TLB TABLE
• • This table is used by the cpu boot code to setup the initial tlb
• • entries. Rather than make broad assumptions in the cpu source tree,
• • this table lets each board set things up however they like.
• • Pointer to the table is returned in r1
• *************************************************************************/
• .section .bootpg,"ax"
• .globl tlbtab

+tlbtab:

• tlbtab_start
• /*

• * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
  

• * use the speed up boot process. It is patched after relocation to
  

• * enable SA_I
  

• */
  

• tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,

• 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
  

• /*

• * TLB entries for SDRAM are not needed on this platform.
  

• * They are dynamically generated in the SPD DDR(2) detection
  

• * routine.
  

• */
  

+#ifdef CONFIG_SYS_INIT_RAM_DCACHE

• /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
• tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,

• 0, AC_R|AC_W|AC_X|SA_G)
  

+#endif

• tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,

• AC_R|AC_W|SA_G|SA_I)
  

• tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,

• AC_R|AC_W|SA_G|SA_I)
  

• /* TLB-entry for NVRAM */
• tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,

• AC_R|AC_W|SA_G|SA_I)
  

• /* TLB-entry for UART */
• tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,

• AC_R|AC_W|SA_G|SA_I)
  

• /* TLB-entry for IO */
• tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,

• AC_R|AC_W|SA_G|SA_I)
  

• /* TLB-entry for OCM */
• tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,

• AC_R|AC_W|AC_X|SA_I)
  

• /* TLB-entry for Local Configuration registers => peripherals */
• tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,

• 4, AC_R|AC_W|AC_X|SA_G|SA_I)
  

• /* AHB: Internal USB Peripherals (USB, SATA) */
• tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,

• AC_R|AC_W|AC_X|SA_G|SA_I)
  

• tlbtab_end

diff --git a/board/gdsys/compactcenter/u-boot.lds b/board/gdsys/compactcenter/u-boot.lds new file mode 100644 index 0000000..0c95d5c --- /dev/null +++ b/board/gdsys/compactcenter/u-boot.lds @@ -0,0 +1,144 @@ +/*

• • (C) Copyright 2008
• • Wolfgang Denk, DENX Software Engineering, wd@denx.de.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf?

• __DYNAMIC = 0; */

+SECTIONS +{

• .resetvec 0xFFFFFFFC :
• {
• *(.resetvec)
• } = 0xffff
• .bootpg 0xFFFFF000 :
• {
• cpu/ppc4xx/start.o (.bootpg)
• } = 0xffff
• /* Read-only sections, merged into text segment: */
• . = + SIZEOF_HEADERS;
• .interp : { *(.interp) }
• .hash : { *(.hash) }
• .dynsym : { *(.dynsym) }
• .dynstr : { *(.dynstr) }
• .rel.text : { *(.rel.text) }
• .rela.text : { *(.rela.text) }
• .rel.data : { *(.rel.data) }
• .rela.data : { *(.rela.data) }
• .rel.rodata : { *(.rel.rodata) }
• .rela.rodata : { *(.rela.rodata) }
• .rel.got : { *(.rel.got) }
• .rela.got : { *(.rela.got) }
• .rel.ctors : { *(.rel.ctors) }
• .rela.ctors : { *(.rela.ctors) }
• .rel.dtors : { *(.rel.dtors) }
• .rela.dtors : { *(.rela.dtors) }
• .rel.bss : { *(.rel.bss) }
• .rela.bss : { *(.rela.bss) }
• .rel.plt : { *(.rel.plt) }
• .rela.plt : { *(.rela.plt) }
• .init : { *(.init) }
• .plt : { *(.plt) }
• .text :
• {
• /* WARNING - the following is hand-optimized to fit within */
• /* the sector layout of our flash chips! XXX FIXME XXX */
• cpu/ppc4xx/start.o (.text)
• board/gdsys/compactcenter/init.o (.text)
• *(.text)
• *(.fixup)
• *(.got1)
• }
• _etext = .;
• PROVIDE (etext = .);
• .rodata :
• {
• *(.rodata)
• *(.rodata1)
• *(.rodata.str1.4)
• }
• .fini : { *(.fini) } =0
• .ctors : { *(.ctors) }
• .dtors : { *(.dtors) }
• /* Read-write section, merged into data segment: */
• . = (. + 0x00FF) & 0xFFFFFF00;
• _erotext = .;
• PROVIDE (erotext = .);
• .reloc :
• {
• *(.got)
• _GOT2_TABLE_ = .;
• *(.got2)
• _FIXUP_TABLE_ = .;
• *(.fixup)
• }
• __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
• __fixup_entries = (. - _FIXUP_TABLE_)>>2;
• .data :
• {
• *(.data)
• *(.data1)
• *(.sdata)
• *(.sdata2)
• *(.dynamic)
• CONSTRUCTORS
• }
• _edata = .;
• PROVIDE (edata = .);
• . = .;
• __u_boot_cmd_start = .;
• .u_boot_cmd : { *(.u_boot_cmd) }
• __u_boot_cmd_end = .;
• . = .;
• __start___ex_table = .;
• __ex_table : { *(__ex_table) }
• __stop___ex_table = .;
• . = ALIGN(256);
• __init_begin = .;
• .text.init : { *(.text.init) }
• .data.init : { *(.data.init) }
• . = ALIGN(256);
• __init_end = .;
• __bss_start = .;
• .bss (NOLOAD) :
• {
• *(.sbss) *(.scommon)
• *(.dynbss)
• *(.bss)
• *(COMMON)
• . = ALIGN(4);
• }
• _end = . ;
• PROVIDE (end = .);

+} diff --git a/include/configs/compactcenter.h b/include/configs/compactcenter.h new file mode 100644 index 0000000..994f218 --- /dev/null +++ b/include/configs/compactcenter.h @@ -0,0 +1,430 @@ +/*

• • (C) Copyright 2009
• • Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
• • Based on include/configs/canyonlands.h
• • (C) Copyright 2008
• • Stefan Roese, DENX Software Engineering, sr@denx.de.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+/*

• • compactcenter.h - configuration for CompactCenter (460EX)
• */

+#ifndef __CONFIG_H +#define __CONFIG_H

+/*

• • High Level Configuration Options
• */

+/*

• • This config file is used for CompactCenter and DevCon-Center
• */

+#define CONFIG_460EX 1 /* Specific PPC460EX */ +#ifdef CONFIG_DEVCONCENTER +#define CONFIG_HOSTNAME devconcenter +#define CONFIG_IDENT_STRING " devconcenter 0.02" +#else +#define CONFIG_HOSTNAME compactcenter +#define CONFIG_IDENT_STRING " compactcenter 0.02" +#endif +#define CONFIG_440 1 +#define CONFIG_4xx 1 /* ... PPC4xx family */

+/*

• • Include common defines/options for all AMCC eval boards
• */

+#include "amcc-common.h"

+#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */

+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_FIT +#define CFG_ALT_MEMTEST

+/*

• • Base addresses -- Note these are effective addresses where the
• • actual resources get mapped (not physical addresses)
• */

+#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE

+/* EBC stuff */ +#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */ +#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* later mapped here */ +#define CONFIG_SYS_FLASH_SIZE (128 << 20) +#else +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */ +#define CONFIG_SYS_FLASH_SIZE (64 << 20) +#endif

+#define CONFIG_SYS_NVRAM_BASE 0xE0000000 +#define CONFIG_SYS_UART_BASE 0xE0100000 +#define CONFIG_SYS_IO_BASE 0xE0200000

+#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ +#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 +#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */ +#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000 +#else +#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000 +#endif +#define CONFIG_SYS_FLASH_BASE_PHYS \

• (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
• | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)

+#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ +#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000

+#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */

+#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */

+/*

• • Initial RAM & stack pointer (placed in OCM)
• */

+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \

• (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)

+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET

+/*

• • Serial Port
• */

+#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */

+/*

• • Environment
• */

+/*

• • Define here the location of the environment variables (FLASH).
• */

+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */

+/*

• • FLASH related
• */

+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */

+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#ifdef CONFIG_DEVCONCENTER +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max num of sectors per chip*/ +#else +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ +#endif

+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */

+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buff'd writes (20x faster) */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */

+#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */

+/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */

+/*

• • DDR SDRAM
• */

+#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */

+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ +#undef CONFIG_PPC4xx_DDR_METHOD_A

+/* DDR1/2 SDRAM Device Control Register Data Values */ +/* Memory Queue */ +#define CONFIG_SYS_SDRAM_R0BAS 0x0000f800 +#define CONFIG_SYS_SDRAM_R1BAS 0x00000000 +#define CONFIG_SYS_SDRAM_R2BAS 0x00000000 +#define CONFIG_SYS_SDRAM_R3BAS 0x00000000 +#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000 +#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008 +#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C80 +#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 +#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000

+/* SDRAM Controller */ +#define CONFIG_SYS_SDRAM0_MB0CF 0x00000201 +#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000 +#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000 +#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000 +#define CONFIG_SYS_SDRAM0_MCOPT1 0x05122000 +#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT0 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT1 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT2 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT3 0x00000000 +#define CONFIG_SYS_SDRAM0_CODT 0x00000020 +#define CONFIG_SYS_SDRAM0_RTR 0x06180000 +#define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000 +#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400 +#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000 +#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000 +#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010000 +#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542 +#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400 +#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000 +#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000 +#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000 +#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000 +#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442 +#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010380 +#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010000 +#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000 +#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000 +#define CONFIG_SYS_SDRAM0_RQDC 0x80000038 +#define CONFIG_SYS_SDRAM0_RFDC 0x003F0000 +#define CONFIG_SYS_SDRAM0_RDCC 0x80000000 +#define CONFIG_SYS_SDRAM0_DLCR 0x00000000 +#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000 +#define CONFIG_SYS_SDRAM0_WRDTR 0x84000800 +#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000 +#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232 +#define CONFIG_SYS_SDRAM0_SDTR3 0x090B0D15 +#define CONFIG_SYS_SDRAM0_MMODE 0x00000442 +#define CONFIG_SYS_SDRAM0_MEMODE 0x00000000

+#define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */

+/*

• • I2C
• */

+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */

+#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

+/* I2C SYSMON */ +#define CONFIG_DTT_LM63 1 /* National LM63 */ +#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ +#define CONFIG_DTT_PWM_LOOKUPTABLE \

• { { 40, 10 }, { 50, 20 }, { 60, 40 } }

+#define CONFIG_DTT_TACH_LIMIT 0xa10

+/* RTC configuration */ +#define CONFIG_RTC_DS1337 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68

+/*

• • Ethernet
• */

+#define CONFIG_IBM_EMAC4_V4 1

+#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1

+#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 3

+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_DYNAMIC_ANEG 1

+/*

• • USB-OHCI
• */

+#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_STORAGE +#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors*/ +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */ +#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */ +#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000) +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15

+/*

• • Default environment variables
• */

+#define CONFIG_EXTRA_ENV_SETTINGS \

• CONFIG_AMCC_DEF_ENV \
• CONFIG_AMCC_DEF_ENV_POWERPC \
• CONFIG_AMCC_DEF_ENV_NOR_UPD \
• "kernel_addr=fc000000\0" \
• "fdt_addr=fc1e0000\0" \
• "ramdisk_addr=fc200000\0" \
• "pciconfighost=1\0" \
• "pcie_mode=RP:RP\0" \
• ""

+/*

• • Commands additional to the ones defined in amcc-common.h
• */

+#define CONFIG_CMD_DATE +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB

+/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION

+/*

• • PCI stuff
• */

+/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_DISABLE_PCIE

+/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ +#undef CONFIG_SYS_PCI_MASTER_INIT

+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */

+/*

• • External Bus Controller (EBC) Setup
• */

+/*

• • CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
• • boot EBC mapping only supports a maximum of 16MBytes
• • (4.ff00.0000 - 4.ffff.ffff).
• • To solve this problem, the FLASH has to get remapped to another
• • EBC address which accepts bigger regions:
• • 0xfc00.0000 -> 4.cc00.0000
• */

+/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x10055e00 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)

+/* Memory Bank 1 (NVRAM) initialization */ +#define CONFIG_SYS_EBC_PB1AP 0x02815480 +/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/ +#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000)

+/* Memory Bank 2 (UART) initialization */ +#define CONFIG_SYS_EBC_PB2AP 0x02815480 +/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/ +#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000)

+/* Memory Bank 3 (IO) initialization */ +#define CONFIG_SYS_EBC_PB3AP 0x02815480 +/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/ +#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000)

+/*

• • PPC4xx GPIO Configuration
• */

+/* 460EX: Use USB configuration */ +#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \ +}, \ +{ \ +/* GPIO Core 1 */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ +{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 USB_SERVICE_SUSPEND_N */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51 SPI_CSS_N */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 FPGA_PROGRAM_UC_N */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 FPGA_INIT_UC_N */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54 WD_STROBE */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 LED_2_OUT */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56 LED_1_OUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61 STARTUP_FINISHED_N */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62 STARTUP_FINISHED */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 SERVICE_PORT_ACTIVE */ \ +} \ +}

+#endif /* __CONFIG_H */