Hi Edward,
On 08/11/2013 10:35, Edward Lin wrote:
Signed-off-by: Edward Lin edward.lin@technexion.com
arch/arm/include/asm/arch-mx6/mx6_ddr_regs.h | 167 +++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx6/mx6_ddr_regs.h
diff --git a/arch/arm/include/asm/arch-mx6/mx6_ddr_regs.h b/arch/arm/include/asm/arch-mx6/mx6_ddr_regs.h new file mode 100644 index 0000000..dd5e892 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6_ddr_regs.h @@ -0,0 +1,167 @@ +/*
- Copyright (C) 2013 TechNexion Inc.
- Author: Edward Lin edward.lin@technexion.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __ASM_ARCH_MX6_DDR_REGS_H__ +#define __ASM_ARCH_MX6_DDR_REGS_H__
+#define MX6_MMDC_P0_BASE 0x021b0000 +#define MX6_MMDC_P1_BASE 0x021b4000
+/* MMDC P0/P1 Registers */ +struct mmdc_p_regs {
u32 mdctl;u32 mdpdc;u32 mdotc;u32 mdcfg0;u32 mdcfg1;u32 mdcfg2;u32 mdmisc;
Ok - if these structure is to make it available for other components, it should replace the structure esd_mmdc_regs in cpu.c. We cannot have both.
u32 res10[25];u32 mpmur0;+}__attribute__((packed, aligned(4)));
I am missing why the packed is needed.
+#define MX6Q_IOM_DDR_BASE 0x020e0500 +struct mx6q_iomux_ddr_regs {
u32 res1[3];u32 dram_sdqs5;u32 dram_dqm5;u32 dram_dqm4;u32 dram_sdqs4;u32 dram_sdqs3;u32 dram_dqm3;u32 dram_sdqs2;u32 dram_dqm2;u32 res2[16];u32 dram_cas;u32 res3[2];u32 dram_ras;u32 dram_reset;u32 res4[2];u32 dram_sdclk_0;u32 dram_sdba2;u32 dram_sdcke0;u32 dram_sdclk_1;u32 dram_sdcke1;u32 dram_sdodt0;u32 dram_sdodt1;u32 res5;u32 dram_sdqs0;u32 dram_dqm0;u32 dram_sdqs1;u32 dram_dqm1;u32 dram_sdqs6;u32 dram_dqm6;u32 dram_sdqs7;u32 dram_dqm7;+}__attribute__((packed, aligned(4)));
+#define MX6Q_IOM_GRP_BASE 0x020e0700 +struct mx6q_iomux_grp_regs {
u32 res1[18];u32 grp_b7ds;u32 grp_addds;u32 grp_ddrmode_ctl;u32 res2;u32 grp_ddrpke;u32 res3[6];u32 grp_ddrmode;u32 res4[3];u32 grp_b0ds;u32 grp_b1ds;u32 grp_ctlds;u32 res5;u32 grp_b2ds;u32 grp_ddr_type;u32 grp_b3ds;u32 grp_b4ds;u32 grp_b5ds;u32 grp_b6ds;+}__attribute__((packed, aligned(4)));
+#define MX6DL_IOM_DDR_BASE 0x020e0400 +struct mx6dl_iomux_ddr_regs {
u32 res1[25];u32 dram_cas;u32 res2[2];u32 dram_dqm0;u32 dram_dqm1;u32 dram_dqm2;u32 dram_dqm3;u32 dram_dqm4;u32 dram_dqm5;u32 dram_dqm6;u32 dram_dqm7;u32 dram_ras;u32 dram_reset;u32 res3[2];u32 dram_sdba2;u32 dram_sdcke0;u32 dram_sdcke1;u32 dram_sdclk_0;u32 dram_sdclk_1;u32 dram_sdodt0;u32 dram_sdodt1;u32 dram_sdqs0;u32 dram_sdqs1;u32 dram_sdqs2;u32 dram_sdqs3;u32 dram_sdqs4;u32 dram_sdqs5;u32 dram_sdqs6;u32 dram_sdqs7;+}__attribute__((packed, aligned(4)));
+#define MX6DL_IOM_GRP_BASE 0x020e0700 +struct mx6dl_iomux_grp_regs {
u32 res1[18];u32 grp_b7ds;u32 grp_addds;u32 grp_ddrmode_ctl;u32 grp_ddrpke;u32 res2[2];u32 grp_ddrmode;u32 grp_b0ds;u32 res3;u32 grp_ctlds;u32 grp_b1ds;u32 grp_ddr_type;u32 grp_b2ds;u32 grp_b3ds;u32 grp_b4ds;u32 grp_b5ds;u32 res4;u32 grp_b6ds;+}__attribute__((packed, aligned(4)));
+#endif
Best regards, Stefano Babic