Enable SPL and binman to generate u-boot.img (machine mode) and u-boot.itb (supervisor mode). DTB is placed at fixed address to ensure that it is 8 byte aligned which is not ensured when dtb is attached behind SPL binary that's why SPL and U-Boot are taking DTB from the same address. Also align addresses for both defconfigs.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/riscv/dts/xilinx-mbv32.dts | 3 +++ board/xilinx/common/board.c | 8 ++++++++ board/xilinx/mbv/Kconfig | 11 +++++++++++ board/xilinx/mbv/board.c | 10 ++++++++++ configs/xilinx_mbv32_defconfig | 18 ++++++++++++++++-- configs/xilinx_mbv32_smode_defconfig | 20 ++++++++++++++++++-- 6 files changed, 66 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 94e42c268115..48ee11549566 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -8,6 +8,9 @@ */
/dts-v1/; + +#include "binman.dtsi" + / { #address-cells = <1>; #size-cells = <1>; diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 9641ed307b75..e5ab32f901b9 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -358,6 +358,14 @@ void *board_fdt_blob_setup(int *err) void *fdt_blob;
*err = 0; + + if (IS_ENABLED(CONFIG_TARGET_XILINX_MBV)) { + fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; + + if (fdt_magic(fdt_blob) == FDT_MAGIC) + return fdt_blob; + } + if (!IS_ENABLED(CONFIG_SPL_BUILD) && !IS_ENABLED(CONFIG_VERSAL_NO_DDR) && !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) { diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index 553c2320697d..9d5ee65cea6f 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -15,12 +15,23 @@ config SYS_CONFIG_NAME config TEXT_BASE default 0x21200000
+config SPL_TEXT_BASE + default 0x20000000 + +config SPL_OPENSBI_LOAD_ADDR + hex + default 0x20200000 + config BOARD_SPECIFIC_OPTIONS def_bool y select GENERIC_RISCV + select SUPPORT_SPL imply BOARD_LATE_INIT + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE imply CMD_SBI imply CMD_PING + imply OF_HAS_PRIOR_STAGE
source "board/xilinx/Kconfig"
diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c index ccf4395d6ace..c478f7e04a0c 100644 --- a/board/xilinx/mbv/board.c +++ b/board/xilinx/mbv/board.c @@ -5,7 +5,17 @@ * Michal Simek michal.simek@amd.com */
+#include <spl.h> + int board_init(void) { return 0; } + +#ifdef CONFIG_SPL +u32 spl_boot_device(void) +{ + /* RISC-V QEMU only supports RAM as SPL boot device */ + return BOOT_DEVICE_RAM; +} +#endif diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index a08a12570d34..4113409efbb2 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -1,10 +1,13 @@ CONFIG_RISCV=y -CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" +CONFIG_SPL_STACK=0x20200000 +CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 CONFIG_DEBUG_UART_CLOCK=1000000 CONFIG_SYS_CLK_FREQ=100000000 @@ -12,18 +15,29 @@ CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_DEBUG_UART=y CONFIG_TARGET_XILINX_MBV=y +# CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_LATE_INIT is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_TIMER=y +# CONFIG_BINMAN_FDT is not set CONFIG_PANIC_HANG=y +CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index fd3ef931f6ca..99381478ac5c 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -1,26 +1,40 @@ CONFIG_RISCV=y -CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" +CONFIG_SPL_STACK=0x20200000 +CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 CONFIG_DEBUG_UART_CLOCK=1000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_TARGET_XILINX_MBV=y +CONFIG_SPL_OPENSBI_LOAD_ADDR=0x20100000 CONFIG_RISCV_SMODE=y +# CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_LATE_INIT is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2 # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_UARTLITE=y CONFIG_DEBUG_UART_ANNOUNCE=y @@ -28,4 +42,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y # CONFIG_RISCV_TIMER is not set CONFIG_XILINX_TIMER=y +# CONFIG_BINMAN_FDT is not set CONFIG_PANIC_HANG=y +CONFIG_SPL_GZIP=y