Add u-boot features to the U-Boot device tree.
Signed-off-by: Hal Feng hal.feng@starfivetech.com --- ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 49 +++++++++++++++++-- arch/riscv/dts/jh7110-u-boot.dtsi | 36 +++++++++++++- 2 files changed, 80 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi index 3012466b30..2b063414e5 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -6,6 +6,10 @@ #include "binman.dtsi" #include "jh7110-u-boot.dtsi" / { + aliases { + spi0 = &qspi; + }; + chosen { bootph-pre-ram; }; @@ -27,42 +31,76 @@
&uart0 { bootph-pre-ram; + reg-offset = <0>; + current-speed = <115200>; + clock-frequency = <24000000>; };
&mmc0 { bootph-pre-ram; + compatible = "snps,dw-mshc"; };
&mmc1 { bootph-pre-ram; + compatible = "snps,dw-mshc"; +}; + +&phy0 { + rx-internal-delay-ps = <1900>; +}; + +&phy1 { + rx-internal-delay-ps = <0>; };
&qspi { bootph-pre-ram; + spi-max-frequency = <250000000>;
- nor-flash@0 { + flash@0 { bootph-pre-ram; + /delete-property/ cdns,read-delay; + spi-max-frequency = <100000000>; }; };
+&syscrg { + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, + <&syscrg JH7110_SYSCLK_BUS_ROOT>, + <&syscrg JH7110_SYSCLK_PERH_ROOT>, + <&syscrg JH7110_SYSCLK_QSPI_REF>; + assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; + assigned-clock-rates = <0>, <0>, <0>, <0>; +}; + +&aoncrg { + assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>; + assigned-clock-parents = <&osc>; + assigned-clock-rates = <0>; +}; + &sysgpio { bootph-pre-ram; };
&mmc0_pins { bootph-pre-ram; - mmc0-pins-rest { + rst-pins { bootph-pre-ram; }; };
&mmc1_pins { bootph-pre-ram; - mmc1-pins0 { + clk-pins { bootph-pre-ram; };
- mmc1-pins1 { + mmc-pins { bootph-pre-ram; }; }; @@ -78,6 +116,9 @@ bootph-pre-ram; eeprom@50 { bootph-pre-ram; + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; }; };
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 2f560e7296..21a2ab1789 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -46,6 +46,15 @@ }; };
+ timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu0_intc 5>, + <&cpu1_intc 5>, + <&cpu2_intc 5>, + <&cpu3_intc 5>, + <&cpu4_intc 5>; + }; + soc { bootph-pre-ram;
@@ -62,7 +71,7 @@ <&syscrg JH7110_SYSRST_DDR_OSC>, <&syscrg JH7110_SYSRST_DDR_APB>; reset-names = "axi", "osc", "apb"; - clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; clock-names = "pll1_out"; clock-frequency = <2133>; }; @@ -73,10 +82,35 @@ bootph-pre-ram; };
+&gmac0_rgmii_rxin { + bootph-pre-ram; +}; + &gmac0_rmii_refin { bootph-pre-ram; };
+&gmac1_rgmii_rxin { + bootph-pre-ram; +}; + +&gmac1_rmii_refin { + bootph-pre-ram; +}; + +&stmmac_axi_setup { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <4>; +}; + +&gmac0 { + snps,perfect-filter-entries = <8>; +}; + +&gmac1 { + snps,perfect-filter-entries = <8>; +}; + &aoncrg { bootph-pre-ram; };