Dear Steven,
in message 3F85960E.60104@imc-berlin.de you wrote:
the patch attached adds support for ALTERA FPGAs. For now only the ACEX1K using the so called "passive serial" Interface.
The code and idea is heavily stolen from the xilinx stuff. And just like there the board specific code has to provide some functions for handling the FPGA signals CONF_DONE, DATA, DCLK, nCONFIG, nSTATUS.
I thought I release it quite early to avoid redundant work done by others and hope this could be a usefull starting point for people using Altera FPGAs.
- Patch by Steven Scholz, 10 Oct 2003
- Add support for Altera FPGA ACEX1K
Mostly added. There is a small bug in the patch, which I tried to fix:
Index: common/Makefile =================================================================== RCS file: /cvsroot/u-boot/u-boot/common/Makefile,v retrieving revision 1.10 diff -p -u -r1.10 Makefile --- common/Makefile 27 Jul 2003 00:21:15 -0000 1.10 +++ common/Makefile 9 Oct 2003 16:50:34 -0000 @@ -47,7 +47,8 @@ COBJS = main.o altera.o bedbug.o \ hush.o kgdb.o lists.o lynxkdi.o miiphybb.o miiphyutil.o \ s_record.o soft_i2c.o soft_spi.o spartan2.o \ usb.o usb_kbd.o usb_storage.o \ - virtex2.o xilinx.o + virtex2.o xilinx.o \ + altera.o ACEX1K.o
You add "altera.o" which is already present in the list of objects ? [Also you ignore ordering :-( ]
Added, thanks. Will show up on CVS soon.
Best regards,
Wolfgang Denk