From: Paul Burton paul.burton@imgtec.com
Add support for the Creator CI20 platform based on the JZ4780 SoC. The DTS file comes from Linux 4.6 as of revision 78800558d104e003f9ae92e0107f1de39cf9de9f
So far, there are still a few details which will have to be fixed once they are fleshed out in Linux: - pinmux: Thus far, this board just pokes the pinmux registers to set the pinmux. For MMC in SPL, this will have to stay. But for full u-boot a proper pinmux driver will have to be added once the pinmux semantics in DT are in mainline Linux. - ethernet,efuse: DT bindings are missing from mainline Linux.
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Paul Burton paul.burton@imgtec.com --- arch/mips/dts/Makefile | 1 + arch/mips/dts/ci20.dts | 114 ++++++++++++++ arch/mips/mach-jz47xx/Kconfig | 11 ++ board/imgtec/ci20/Kconfig | 15 ++ board/imgtec/ci20/Makefile | 5 + board/imgtec/ci20/README | 10 ++ board/imgtec/ci20/ci20.c | 354 ++++++++++++++++++++++++++++++++++++++++++ configs/ci20_defconfig | 19 +++ include/configs/ci20.h | 122 +++++++++++++++ 9 files changed, 651 insertions(+) create mode 100644 arch/mips/dts/ci20.dts create mode 100644 board/imgtec/ci20/Kconfig create mode 100644 board/imgtec/ci20/Makefile create mode 100644 board/imgtec/ci20/README create mode 100644 board/imgtec/ci20/ci20.c create mode 100644 configs/ci20_defconfig create mode 100644 include/configs/ci20.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 2f04d73..121ab83 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_TARGET_AP143) += ap143.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb +dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts new file mode 100644 index 0000000..9dab5e6 --- /dev/null +++ b/arch/mips/dts/ci20.dts @@ -0,0 +1,114 @@ +/dts-v1/; + +#include "jz4780.dtsi" + +/ { + compatible = "img,ci20", "ingenic,jz4780"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000 + 0x30000000 0x30000000>; + }; +}; + +&ext { + clock-frequency = <48000000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&nemc { + status = "okay"; + + nandc: nand-controller@1 { + compatible = "ingenic,jz4780-nand"; + reg = <1 0 0x1000000>; + + #address-cells = <1>; + #size-cells = <0>; + + ingenic,bch-controller = <&bch>; + + ingenic,nemc-tAS = <10>; + ingenic,nemc-tAH = <5>; + ingenic,nemc-tBP = <10>; + ingenic,nemc-tAW = <15>; + ingenic,nemc-tSTRV = <100>; + + nand@1 { + reg = <1>; + + nand-ecc-step-size = <1024>; + nand-ecc-strength = <24>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x0 0x0 0x800000>; + }; + + partition@0x800000 { + label = "u-boot"; + reg = <0x0 0x800000 0x0 0x200000>; + }; + + partition@0xa00000 { + label = "u-boot-env"; + reg = <0x0 0xa00000 0x0 0x200000>; + }; + + partition@0xc00000 { + label = "boot"; + reg = <0x0 0xc00000 0x0 0x4000000>; + }; + + partition@0x8c00000 { + label = "system"; + reg = <0x0 0x4c00000 0x1 0xfb400000>; + }; + }; + }; + }; +}; + +&bch { + status = "okay"; +}; + +&msc0 { + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; diff --git a/arch/mips/mach-jz47xx/Kconfig b/arch/mips/mach-jz47xx/Kconfig index cd6944c..dcaac01 100644 --- a/arch/mips/mach-jz47xx/Kconfig +++ b/arch/mips/mach-jz47xx/Kconfig @@ -12,4 +12,15 @@ config SOC_JZ4780 help Support for Ingenic JZ4780 family SoCs.
+choice + prompt "Board select" + +config TARGET_JZ4780_CI20 + bool "Creator CI20 Reference Board" + select SOC_JZ4780 + +endchoice + +source "board/imgtec/ci20/Kconfig" + endmenu diff --git a/board/imgtec/ci20/Kconfig b/board/imgtec/ci20/Kconfig new file mode 100644 index 0000000..82bf65d --- /dev/null +++ b/board/imgtec/ci20/Kconfig @@ -0,0 +1,15 @@ +if TARGET_JZ4780_CI20 + +config SYS_BOARD + default "ci20" + +config SYS_VENDOR + default "imgtec" + +config SYS_CONFIG_NAME + default "ci20" + +config SYS_TEXT_BASE + default 0x80000000 + +endif diff --git a/board/imgtec/ci20/Makefile b/board/imgtec/ci20/Makefile new file mode 100644 index 0000000..8c00081 --- /dev/null +++ b/board/imgtec/ci20/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ci20.o diff --git a/board/imgtec/ci20/README b/board/imgtec/ci20/README new file mode 100644 index 0000000..c757d41 --- /dev/null +++ b/board/imgtec/ci20/README @@ -0,0 +1,10 @@ +CI20 U-Boot + +Installation to an SD card: + Repartition your card with an MBR such that the first partition starts at an + offset of no less than 270KB. Then install U-Boot SPL & the full U-Boot image + to the card like so: + + dd if=spl/u-boot-spl.bin of=/dev/sdX obs=512 seek=1 + dd if=u-boot.img of=/dev/sdX obs=1K seek=14 + sync diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c new file mode 100644 index 0000000..bbbad78 --- /dev/null +++ b/board/imgtec/ci20/ci20.c @@ -0,0 +1,354 @@ +/* + * CI20 setup code + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton paul.burton@imgtec.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <net.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <mach/jz4780.h> +#include <mach/jz4780_dram.h> + +#define JZ_GPIO(bank, pin) ((32 * (bank)) + (pin)) + +struct ci20_otp { + u32 serial_number; + u32 date; + u8 manufacturer[2]; + u8 mac[6]; +} __packed; + +static void ci20_mux_eth(void) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + +#ifdef CONFIG_NAND + /* setup pins (some already setup for NAND) */ + writel(0x04030000, gpio_regs + GPIO_PXINTC(0)); + writel(0x04030000, gpio_regs + GPIO_PXMASKC(0)); + writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0)); + writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0)); + writel(0x04030000, gpio_regs + GPIO_PXPENS(0)); +#else + /* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */ + writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0)); + writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0)); + writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0)); + writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0)); + writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0)); + writel(0x00000003, gpio_regs + GPIO_PXINTC(1)); + writel(0x00000003, gpio_regs + GPIO_PXMASKC(1)); + writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1)); + writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1)); + writel(0x00000003, gpio_regs + GPIO_PXPENS(1)); +#endif +} + +static void ci20_mux_jtag(void) +{ +#ifdef CONFIG_JTAG + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + + /* enable JTAG */ + writel(3 << 30, gpio_regs + GPIO_PXINTC(0)); + writel(3 << 30, gpio_regs + GPIO_PXMASKC(0)); + writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0)); + writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0)); +#endif +} + +static void ci20_mux_mmc(void) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + + /* setup MSC1 pins */ + writel(0x30f00000, gpio_regs + GPIO_PXINTC(4)); + writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4)); + writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4)); + writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4)); + writel(0x30f00000, gpio_regs + GPIO_PXPENC(4)); + jz4780_clk_ungate_mmc(); +} + +static void ci20_mux_nand(void) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + + /* setup pins */ + writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0)); + writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0)); + writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0)); + writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0)); + writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0)); + writel(0x00000003, gpio_regs + GPIO_PXINTC(1)); + writel(0x00000003, gpio_regs + GPIO_PXMASKC(1)); + writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1)); + writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1)); + writel(0x00000003, gpio_regs + GPIO_PXPENS(1)); + + /* FRB0_N */ + gpio_direction_input(32 * 0 + 20); + writel(20, gpio_regs + GPIO_PXPENS(0)); + + /* disable write protect */ + gpio_direction_output(JZ_GPIO(5, 22), 1); +} + +static void ci20_mux_uart(void) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + + /* UART0 */ + writel(0x9, gpio_regs + GPIO_PXINTC(5)); + writel(0x9, gpio_regs + GPIO_PXMASKC(5)); + writel(0x9, gpio_regs + GPIO_PXPAT1C(5)); + writel(0x9, gpio_regs + GPIO_PXPAT0C(5)); + writel(0x9, gpio_regs + GPIO_PXPENC(5)); + jz4780_clk_ungate_uart(0); + + /* UART 1 and 2 */ + jz4780_clk_ungate_uart(1); + jz4780_clk_ungate_uart(2); + +#ifndef CONFIG_JTAG + /* UART3 */ + writel(1 << 12, gpio_regs + GPIO_PXINTC(3)); + writel(1 << 12, gpio_regs + GPIO_PXMASKS(3)); + writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3)); + writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3)); + writel(3 << 30, gpio_regs + GPIO_PXINTC(0)); + writel(3 << 30, gpio_regs + GPIO_PXMASKC(0)); + writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0)); + writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0)); + writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0)); + jz4780_clk_ungate_uart(3); +#endif + + /* UART4 */ + writel(0x100400, gpio_regs + GPIO_PXINTC(2)); + writel(0x100400, gpio_regs + GPIO_PXMASKC(2)); + writel(0x100400, gpio_regs + GPIO_PXPAT1S(2)); + writel(0x100400, gpio_regs + GPIO_PXPAT0C(2)); + writel(0x100400, gpio_regs + GPIO_PXPENC(2)); + jz4780_clk_ungate_uart(4); +} + +int board_early_init_f(void) +{ + ci20_mux_jtag(); + ci20_mux_uart(); + + ci20_mux_eth(); + ci20_mux_mmc(); + ci20_mux_nand(); + + /* SYS_POWER_IND high (LED blue, VBUS on) */ + gpio_direction_output(JZ_GPIO(5, 15), 1); + + /* LEDs off */ + gpio_direction_output(JZ_GPIO(2, 0), 0); + gpio_direction_output(JZ_GPIO(2, 0), 0); + gpio_direction_output(JZ_GPIO(2, 0), 0); + gpio_direction_output(JZ_GPIO(2, 0), 0); + + return 0; +} + +int misc_init_r(void) +{ + const u32 efuse_clk = jz4780_clk_get_efuse_clk(); + struct ci20_otp otp; + char manufacturer[3]; + + /* Read the board OTP data */ + jz4780_efuse_init(efuse_clk); + jz4780_efuse_read(0x18, 16, (u8 *)&otp); + + /* Set MAC address */ + if (!is_valid_ethaddr(otp.mac)) { + /* no MAC assigned, generate one from the unique chip ID */ + jz4780_efuse_read(0x8, 4, &otp.mac[0]); + jz4780_efuse_read(0x12, 2, &otp.mac[4]); + otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01; + } + eth_setenv_enetaddr("ethaddr", otp.mac); + + /* Put other board information into the environment */ + setenv_ulong("serial#", otp.serial_number); + setenv_ulong("board_date", otp.date); + manufacturer[0] = otp.manufacturer[0]; + manufacturer[1] = otp.manufacturer[1]; + manufacturer[2] = 0; + setenv("board_mfr", manufacturer); + + return 0; +} + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + /* Enable clock */ + jz4780_clk_ungate_ethernet(); + + /* Enable power (PB25) */ + gpio_direction_output(JZ_GPIO(1, 25), 1); + + /* Reset (PF12) */ + mdelay(10); + gpio_direction_output(JZ_GPIO(5, 12), 0); + mdelay(10); + gpio_direction_output(JZ_GPIO(5, 12), 1); + mdelay(10); + + return dm9000_initialize(bis); +} +#endif /* CONFIG_DRIVER_DM9000 */ + +static u8 ci20_revision(void) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int val; + + gpio_direction_input(82); + gpio_direction_input(83); + + /* Enable pullups */ + writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2)); + + /* Read PC18/19 for version */ + val = (!!gpio_get_value(82)) | ((!!gpio_get_value(83)) << 1); + + if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */ + return 1; + if (val == 1) /* Rev 2 boards pulldown port C bit 18 giving 1 */ + return 2; + + return 0; +} + +/* U-Boot common routines */ +int checkboard(void) +{ + printf("Board: Creator CI20 (rev.%d)\n", ci20_revision()); + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +#if defined(CONFIG_SPL_MMC_SUPPORT) +int board_mmc_init(bd_t *bd) +{ + ci20_mux_mmc(); + return jz_mmc_init((void __iomem *)MSC0_BASE); +} +#endif + +static const struct jz4780_ddr_config K4B2G0846Q_48_config = { + .timing = { + (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) | + (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT), + + + (4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) | + (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT), + + (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) | + (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) | + (21 << DDRC_TIMING3_TRC_BIT), + + (31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) | + (4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) | + (8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT), + + (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) | + (4 << DDRC_TIMING5_TWDLAT_BIT), + + (25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) | + (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT), + }, + + /* PHY */ + /* Mode Register 0 */ + .mr0 = 0x420, +#ifdef SDRAM_DISABLE_DLL + .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE), +#else + .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS), +#endif + + .ptr0 = 0x002000d4, + .ptr1 = 0x02230d40, + .ptr2 = 0x04013880, + + .dtpr0 = 0x2a8f6690, + .dtpr1 = 0x00400860, + .dtpr2 = 0x10042a00, + + .pullup = 0x0b, + .pulldn = 0x0b, +}; + +static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = { + .timing = { + (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) | + (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT), + + (4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) | + (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT), + + (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) | + (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) | + (22 << DDRC_TIMING3_TRC_BIT), + + (42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) | + (4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) | + (3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT), + + (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) | + (4 << DDRC_TIMING5_TWDLAT_BIT), + + (25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) | + (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT), + }, + + /* PHY */ + /* Mode Register 0 */ + .mr0 = 0x420, +#ifdef SDRAM_DISABLE_DLL + .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE), +#else + .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS), +#endif + + .ptr0 = 0x002000d4, + .ptr1 = 0x02d30d40, + .ptr2 = 0x04013880, + + .dtpr0 = 0x2c906690, + .dtpr1 = 0x005608a0, + .dtpr2 = 0x10042a00, + + .pullup = 0x0e, + .pulldn = 0x0e, +}; + +#if (CONFIG_SYS_MHZ != 1200) || (CONFIG_SYS_EXTAL != 48000000) +#error No DDR configuration for CPU speed +#endif + +const struct jz4780_ddr_config *jz4780_get_ddr_config(void) +{ + const int board_revision = ci20_revision(); + + if (board_revision == 2) + return &K4B2G0846Q_48_config; + else /* Fall back to H5TQ2G83CFR RAM */ + return &H5TQ2G83CFR_48_config; +} +#endif diff --git a/configs/ci20_defconfig b/configs/ci20_defconfig new file mode 100644 index 0000000..3837c02 --- /dev/null +++ b/configs/ci20_defconfig @@ -0,0 +1,19 @@ +CONFIG_MIPS=y +CONFIG_ARCH_JZ47XX=y +CONFIG_TARGET_JZ4780_CI20=y +CONFIG_DEFAULT_DEVICE_TREE="ci20" +CONFIG_SPL=y +CONFIG_FIT=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +# CONFIG_SPL_DM_MMC is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_JZ4780_EFUSE=y +CONFIG_JZ47XX_GPIO=y +CONFIG_JZ47XX_MMC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SERIAL=y diff --git a/include/configs/ci20.h b/include/configs/ci20.h new file mode 100644 index 0000000..820b017 --- /dev/null +++ b/include/configs/ci20.h @@ -0,0 +1,122 @@ +/* + * CI20 configuration + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton paul.burton@imgtec.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_CI20_H__ +#define __CONFIG_CI20_H__ + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_SYS_NO_FLASH +#define CONFIG_LZO + +/* Ingenic JZ4780 clock configuration. */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 1200 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_EXTAL 48000000 /* EXTAL @ 48 MHz */ +#define CONFIG_SYS_MEM_SPEED (CONFIG_SYS_MHZ * 1000000) +#define CONFIG_SYS_MEM_DIV 3 +#define CONFIG_SYS_AUDIO_SPEED (768 * 1000000) + +/* Memory configuration */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x88000000 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 0x8000 +#define CONFIG_SYS_ICACHE_SIZE 0x8000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* Enable JTAG support */ +#define CONFIG_JTAG + +/* NS16550-ish UARTs */ +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_EXTAL +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CONSOLE_MUX +#define CONFIG_BAUDRATE 115200 + +/* Ethernet: davicom DM9000 */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0xb6000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 2) + +/* MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* Environment */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE (32 << 10) +#define CONFIG_ENV_OFFSET ((14 + 512) << 10) +#define CONFIG_ENV_OVERWRITE + +/* Command line configuration. */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Miscellaneous configuration options */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) +#define CONFIG_BOOTARGS "console=ttyS0,115200 rw rootwait" + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */ + +#define CONFIG_SPL_TEXT_BASE 0xf4000a00 +#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00) + +#define CONFIG_SPL_BSS_START_ADDR 0xf4004000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */ + +#define CONFIG_SPL_LDSCRIPT "arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds" +#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx" + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14KB offset */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 /* 512 KB */ + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_USE_TINY_PRINTF +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE +#define CONFIG_MMC_TINY +#undef CONFIG_DM_MMC +#endif + +#endif /* __CONFIG_CI20_H__ */