[U-Boot] [PATCH 28/57] x86: ivybridge: Use driver model PCI API in bd82x6x_pci_init()

Adjust bd82x6x_pci_init() to use the driver model PCI API.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/northbridge.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 2e63552..f6ecba4 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -21,43 +21,43 @@

static int bridge_revision_id = -1;

-static void bd82x6x_pci_init(pci_dev_t dev) +static void bd82x6x_pci_init(struct udevice *dev) { u16 reg16; u8 reg8;

debug("bd82x6x PCI init.\n"); /* Enable Bus Master */ - reg16 = x86_pci_read_config16(dev, PCI_COMMAND); + dm_pci_read_config16(dev, PCI_COMMAND, &reg16); reg16 |= PCI_COMMAND_MASTER; - x86_pci_write_config16(dev, PCI_COMMAND, reg16); + dm_pci_write_config16(dev, PCI_COMMAND, reg16);

/* This device has no interrupt */ - x86_pci_write_config8(dev, INTR, 0xff); + dm_pci_write_config8(dev, INTR, 0xff);

/* disable parity error response and SERR */ - reg16 = x86_pci_read_config16(dev, BCTRL); + dm_pci_read_config16(dev, BCTRL, &reg16); reg16 &= ~(1 << 0); reg16 &= ~(1 << 1); - x86_pci_write_config16(dev, BCTRL, reg16); + dm_pci_write_config16(dev, BCTRL, reg16);

/* Master Latency Count must be set to 0x04! */ - reg8 = x86_pci_read_config8(dev, SMLT); + dm_pci_read_config8(dev, SMLT, &reg8); reg8 &= 0x07; reg8 |= (0x04 << 3); - x86_pci_write_config8(dev, SMLT, reg8); + dm_pci_write_config8(dev, SMLT, reg8);

/* Will this improve throughput of bus masters? */ - x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06); + dm_pci_write_config8(dev, PCI_MIN_GNT, 0x06);

/* Clear errors in status registers */ - reg16 = x86_pci_read_config16(dev, PSTS); + dm_pci_read_config16(dev, PSTS, &reg16); /* reg16 |= 0xf900; */ - x86_pci_write_config16(dev, PSTS, reg16); + dm_pci_write_config16(dev, PSTS, reg16);

- reg16 = x86_pci_read_config16(dev, SECSTS); + dm_pci_read_config16(dev, SECSTS, &reg16); /* reg16 |= 0xf900; */ - x86_pci_write_config16(dev, SECSTS, reg16); + dm_pci_write_config16(dev, SECSTS, reg16); }

int bridge_silicon_revision(void) @@ -284,7 +284,7 @@ static int bd82x6x_northbridge_probe(struct udevice *dev) if (!(gd->flags & GD_FLG_RELOC)) return bd82x6x_northbridge_early_init(dev);

- bd82x6x_pci_init(PCH_DEV); + bd82x6x_pci_init(dev); northbridge_enable(PCH_DEV); northbridge_init(PCH_DEV);