Re: [U-Boot] [PATCH] Revert "net: phy: delay only if reset handler is registered"

Hi Jörg ,

On Thu, Nov 19, 2015 at 6:13 AM, Jörg Krause joerg.krause@embedded.rocks wrote:

Ok, I checked. This is what happens in setup_fec():

1. Enable AR8031 power
2. Assert AR8031 RESET
3. Delay 0.5ms
4. Deassert AR8031 RESET
5. Enable anatop clock

Shouldn't the clock be enabled and become stable before deasserting the RESET line?

...

I have also tried increasing the reset time and still do not have Ethernel functional.

The AR8031 datasheets recommands a delay of 10ms.

Ok, I will test your proposal below on Monday when I get access to my mx6sxsabresd, thanks.

--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -150,11 +150,15 @@ static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg; + int reg, ret;

/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);

+ ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + imx_iomux_v3_setup_multiple_pads(phy_control_pads, ARRAY_SIZE(phy_control_pads));

@@ -163,14 +167,14 @@ static int setup_fec(void)

/* Reset AR8031 PHY */ gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); - udelay(500); + mdelay(10); gpio_set_value(IMX_GPIO_NR(2, 7), 1);

reg = readl(&anatop->pll_enet); reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; writel(reg, &anatop->pll_enet);

- return enable_fec_anatop_clock(0, ENET_125MHZ); + return 0; }

int board_eth_init(bd_t *bis)