Dear Ilya Yanok,
Buffer coming from upper layers should be cacheline aligned/padded to perform safe cache operations. For now we don't do bounce buffering so getting unaligned buffer is an upper layer error. We can't check if the buffer is properly padded with current interface so just assume it is (consider changing with in the future). The following changes are done:
- Remove useless length alignment check. We get actual transfer
length not the size of the underlying buffer so it's perfectly valid for it to be unaligned. 2. Move flush_dcache_range() out of while loop or it will flush too much. 3. Don't try to fix buffer address before calling invalidate: if it's unaligned it's an error anyway so let cache subsystem cry about that. 4. Fix end buffer address to be cacheline aligned assuming upper layer reserved enough space. This is potentially dangerous operation so upper layers should be careful about that.
Signed-off-by: Ilya Yanok ilya.yanok@cogentembedded.com
drivers/usb/host/ehci-hcd.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 59039f4..a6cd5e3 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -175,18 +175,15 @@ static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) { uint32_t delta, next; uint32_t addr = (uint32_t)buf;
size_t rsz = roundup(sz, 32); int idx;
if (sz != rsz)
debug("EHCI-HCD: Misaligned buffer size (%08x)\n", sz);
Shall we not also test if addr + sz is aligned?
- if (addr & 31)
- if (addr != ALIGN(addr, ARCH_DMA_MINALIGN)) debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
[...]
Best regards, Marek Vasut