Hi Sylvain,
On 11.08.2015 23:16, LEMIEUX, SYLVAIN wrote:
Hi Vladimir,
-----Original Message----- From: Vladimir Zapolskiy [mailto:vz@mleia.com] Sent: 11-Aug-15 12:57 PM
A number of LPC32xx SLC NAND defines is dictated by controller hardware limits and OOB layout is defined by operating system, the definitions are common for all users. Since those macro are used in out of NAND SLC driver code (simple NAND SPL framework), they can not be placed into the driver, therefore move them from board config files to arch/config.h
The change also adds OOB layout details specific to small page NAND devices taken from Linux kernel.
Signed-off-by: Vladimir Zapolskiy vz@mleia.com
The change is based on
arch/arm/include/asm/arch-lpc32xx/config.h | 29 +++++++++++++++++++++++++++++ include/configs/devkit3250.h | 14 +++----------- 2 files changed, 32 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index d57bc48..d161ad2 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -55,6 +55,35 @@ /* Ethernet */ #define LPC32XX_ETH_BASE ETHERNET_BASE
+/* NAND */ +#if defined(CONFIG_NAND_LPC32XX_SLC)
[..]
+#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \56, 57, 58, 59, 60, 61, 62, 63, }+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
Should we only move to "config.h", the definition that are use by the NAND SPL framework and the NAND SLC driver?
The following definition are only use by the NAND SPL framework:
- CONFIG_SYS_NAND_ECCPOS
- CONFIG_SYS_NAND_BAD_BLOCK_POS
- CONFIG_SYS_NAND_PAGE_COUNT
The NAND SPL framework uses a longer list of macro definitions (please check the source code, if you wish): * CONFIG_SYS_NAND_BLOCK_SIZE * CONFIG_SYS_NAND_PAGE_SIZE * CONFIG_SYS_NAND_PAGE_COUNT * CONFIG_SYS_NAND_ECCSIZE * CONFIG_SYS_NAND_ECCPOS * CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_OOBSIZE * CONFIG_SYS_NAND_BAD_BLOCK_POS
All of them in the case of large page NAND device are found in https://patchwork.ozlabs.org/patch/497299/ change and the given values are common for all LPC32xx boards utilizing NAND SLC.
Generally I would say that not only the macro related to NAND SPL framework should be moved, but also all the macro dictated by the hardware constraints, e.g. ECC size and bytes, and all the macro shared with other platform users like operating systems, this includes for instance OOB layout and bad block position in OOB.
In other words this list includes everything common among all possible LPC32xx boards with NAND SLC controller enabled, and hopefully this change addresses all such macro. If you find any inconsistencies or missing data in the change, please let me know.
[...]
+#define CONFIG_SYS_NAND_ECCSIZE 0x100 +#define CONFIG_SYS_NAND_ECCBYTES 3
Do you want to change "lpc32xx_nand_slc.c" to use those 2 define as part of this patch or do you prefer I change them as part of the "nand: LPC32xx: add hardware ECC support" patch?
This is fine with me, I would appreciate, if you can rebase 2/5 and 3/5 from your last series on top of this change, it should be guaranteed that the compilation is not broken for devkit3250 board in assumption that all my previously sent patches are applied.
-- With best wishes, Vladimir