Hi Francesco,
On Fri, Dec 3, 2021 at 5:47 AM Francesco Dolcini francesco.dolcini@toradex.com wrote:
I think that this applies even with just one chip select, it is just prescribing a procedure and explicitly saying that it must be done for all the chip select in use, either 1 or 2.
According to the NXP application note: https://www.voipac.com/downloads/imx/test/nxp_doc/AN/AN4467_DDR_Calibration....
"To issue a Precharge-All to CS0, write 0x04000050 to MDSCR."
but such setting is not done in NXP U-Boot for mx6sabresd: https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/mx...
Back to your original instability issue: I suppose you are talking about colibri_imx6.c.
Does it work well if you convert it to the mx6_dram_cfg() scheme?