Subject: Re: [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.
On 07/03/2014 12:51 PM, Xiubo Li wrote:
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency.
Can you give an example?
In LS1021A-QDS/TWR, the CONFIG_SYS_CLK_FREQ is 100Mhz and the ARCH timer's Frequency will be 12.5Mhz...
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com
arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S
b/arch/arm/cpu/armv7/nonsec_virt.S
index 6f90988..e9766c0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -147,11 +147,11 @@ ENTRY(_nonsec_init)
- we do this here instead.
- But first check if we have the generic timer.
*/ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ
Aren't you breaking the boards which rely on CONFIG_SYS_CLK_FREQ ?
I hadn't found any board is using this in the upstreamed tree, or may I miss something ?
If there exist some, and I will redefined it for them here.
In ARMv7, what could I find is that only vexpress_ca15_tc2 board has enabled the CONFIG_ARMV7_VIRT without defining it.
Thanks,
BRs Xiubo
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
- ldreq r1, =CONFIG_SYS_CLK_FREQ
- ldreq r1, =CONFIG_TIMER_CLK_FREQ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif
Diana