Re: [U-Boot] [PATCH v5 01/16] arm: socfpga: Restructure clock manager driver

On 04/13/2017 07:41 PM, Ley Foon Tan wrote:

Restructure clock manager driver in the preparation to support A10. Move the Gen5 specific code to _gen5 files.

• Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
• Check return value from wait_for_bit(). So change return type to int for cm_write_with_phase() and cm_basic_init().

Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com

[...]

/* function to write a clock register that has phase information */ -static void cm_write_with_phase(uint32_t value,

• 		uint32_t reg_address, uint32_t mask)
  

+static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask) {

• int ret;
• /* poll until phase is zero */

• while (readl(reg_address) & mask)

• ;
  

• ret = wait_for_bit(__func__, (const u32 *)reg_address, mask,

• 	   false, 20000, false);
  

• if (ret)

• return ret;
  
  

  writel(value, reg_address);

• while (readl(reg_address) & mask)

• ;
  

• return wait_for_bit(__func__, (const u32 *)reg_address, mask,

• 	    false, 20000, false);
  

}

Could it be that this active wait is here so that it'd work without an initialized timer ? Because at this point, you don't have timer and I think wait_for_bit() uses timer.