On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
Add MMU support for Stratix SoC
You could get more creative with the commit messages ;-)
Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
Acked-by: Marek Vasut marex@denx.de
arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 43e18d2..098e5e9 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o obj-y += mailbox_s10.o obj-y += misc_s10.o +obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_s10.o obj-y += wrap_pinmux_config_s10.o diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c new file mode 100644 index 0000000..670ceb9 --- /dev/null +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
- */
+#include <common.h> +#include <asm/armv8/mmu.h>
+DECLARE_GLOBAL_DATA_PTR;
+static struct mm_region socfpga_stratix10_mem_map[] = {
- {
/* MEM 2GB*/.virt = 0x0UL,.phys = 0x0UL,.size = 0x80000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_INNER_SHARE,- }, {
/* FPGA 1.5GB */.virt = 0x80000000UL,.phys = 0x80000000UL,.size = 0x60000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN | PTE_BLOCK_UXN,- }, {
/* DEVICE 142MB */.virt = 0xF7000000UL,.phys = 0xF7000000UL,.size = 0x08E00000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN | PTE_BLOCK_UXN,- }, {
/* OCRAM 1MB but available 256KB */.virt = 0xFFE00000UL,.phys = 0xFFE00000UL,.size = 0x00100000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_INNER_SHARE,- }, {
/* DEVICE 32KB */.virt = 0xFFFC0000UL,.phys = 0xFFFC0000UL,.size = 0x00008000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN | PTE_BLOCK_UXN,- }, {
/* MEM 124GB */.virt = 0x0100000000UL,.phys = 0x0100000000UL,.size = 0x1F00000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_INNER_SHARE,- }, {
/* DEVICE 4GB */.virt = 0x2000000000UL,.phys = 0x2000000000UL,.size = 0x0100000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN | PTE_BLOCK_UXN,- }, {
/* List terminator */- },
+};
+struct mm_region *mem_map = socfpga_stratix10_mem_map;