Fix english, use "SoCFPGA" spelling, add pointer for help with installation.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/doc/README.socfpga b/doc/README.socfpga index cfcbbfe..b43704e 100644 --- a/doc/README.socfpga +++ b/doc/README.socfpga @@ -1,18 +1,18 @@
-------------------------------------------- -SOCFPGA Documentation for U-Boot and SPL +SoCFPGA Documentation for U-Boot and SPL --------------------------------------------
This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore -based SOCFPGA. To know more about the hardware itself, please refer to +based SoCFPGA. To know more about the hardware itself, please refer to www.altera.com.
-------------------------------------------- socfpga_dw_mmc -------------------------------------------- -Here are macro and detailed configuration required to enable DesignWare SDMMC -controller support within SOCFPGA +Here are macros and detailed configuration required to enable DesignWare SDMMC +controller support within SoCFPGA:
#define CONFIG_MMC -> To enable the SD MMC framework support @@ -30,10 +30,10 @@ controller support within SOCFPGA -> Enable the common DesignWare SDMMC controller framework
#define CONFIG_SOCFPGA_DWMMC --> Enable the SOCFPGA specific driver for DesignWare SDMMC controller +-> Enable the SoCFPGA specific driver for DesignWare SDMMC controller
#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 --> The FIFO depth for SOCFPGA DesignWare SDMMC controller +-> The FIFO depth for SoCFPGA DesignWare SDMMC controller
#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 -> Phase-shifted clock of sdmmc_clk for controller to drive command and data to @@ -43,11 +43,20 @@ is 135 / 360 * 20ns = 7.5ns.
#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 -> Phase-shifted clock of sdmmc_clk used to sample the command and data from -the card +the card.
#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 --> Bus width of data line which either 1, 4 or 8 and based on board routing. +-> Bus width of data line which is either 1, 4 or 8 and is based on board +routing.
#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 -> The clock rate to controller. Do note the controller have a wrapper which divide the clock from PLL by 4. + +-------------------------------- +Installing U-Boot / U-Boot SPL +-------------------------------- + +Boot ROM loads U-Boot SPL from magic partition, (id 0xa2). See +http://xillybus.com/tutorials/u-boot-image-altera-soc . +