On Fri, Oct 14, 2016 at 8:14 AM, Chenhui Zhao z.chenhui@gmail.com wrote:
On Thu, Oct 13, 2016 at 5:52 PM, Chen-Yu Tsai wens@csie.org wrote:
On Sat, Oct 8, 2016 at 7:08 PM, Chenhui Zhao chenhui.zhao@nxp.com wrote:
Save and restore core registers from r4 to r12 so that PSCI code won't break their value.
Signed-off-by: Chenhui Zhao chenhui.zhao@nxp.com Signed-off-by: Alison Wang alison.wang@nxp.com Signed-off-by: Abhimanyu Saini abhimanyu.saini@nxp.com
arch/arm/cpu/armv7/psci.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 6a36208..746297c 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -152,7 +152,7 @@ _psci_table: .word 0
_smc_psci:
push {r4-r7,lr}
push {r4-r12,lr}This change is not needed. This function only uses r4-r7. Any subroutines called should save variable registers (r4-r12) themselves, per the ARM calling conventions.
ChenYu
I do not think it is a normal calling, instead it is an exception handler. In the exception context, it is necessary to save/restore all registers.
It should be the same for an exception handler. You only save the registers that you clobber, at each function level.
ChenYu
Sorry, my mail server has something wrong.
Chenhui
@ Switch to secure mrc p15, 0, r7, c1, c1, 0@@ -175,7 +175,7 @@ _smc_psci: @ Switch back to non-secure 2: mcr p15, 0, r7, c1, c1, 0
pop {r4-r7, lr}
pop {r4-r12, lr} movs pc, lr @ Return to the kernel@ Requires dense and single-cluster CPU ID space
1.9.1
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