Signed-off-by: Matthias Ludwig mludwig@ultratronik.de --- board/omap3/evm/evm.c | 15 +++++++-------- cpu/arm_cortexa8/omap3/mem.c | 21 ++++++++++----------- cpu/arm_cortexa8/omap3/sys_info.c | 3 +-- drivers/mtd/nand/omap_gpmc.c | 33 ++++++++++++++++----------------- 4 files changed, 34 insertions(+), 38 deletions(-)
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c index 33d6509..251f1c5 100644 --- a/board/omap3/evm/evm.c +++ b/board/omap3/evm/evm.c @@ -92,17 +92,16 @@ void set_muxconf_regs(void) static void setup_net_chip(void) { gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; - struct gpmc *gpmc = (struct gpmc *)GPMC_BASE; ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc->cs[5].config1); - writel(NET_GPMC_CONFIG2, &gpmc->cs[5].config2); - writel(NET_GPMC_CONFIG3, &gpmc->cs[5].config3); - writel(NET_GPMC_CONFIG4, &gpmc->cs[5].config4); - writel(NET_GPMC_CONFIG5, &gpmc->cs[5].config5); - writel(NET_GPMC_CONFIG6, &gpmc->cs[5].config6); - writel(NET_GPMC_CONFIG7, &gpmc->cs[5].config7); + writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); + writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); + writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); + writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); + writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); + writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); + writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index e75283b..addf70f 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -41,6 +41,8 @@ unsigned int boot_flash_sec; unsigned int boot_flash_type; volatile unsigned int boot_flash_env_addr;
+struct gpmc *gpmc_cfg; + #if defined(CONFIG_CMD_NAND) static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, @@ -51,8 +53,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG6, 0 };
-struct gpmc *gpmc_cfg; - #if defined(CONFIG_ENV_IS_IN_NAND) #define GPMC_CS 0 #else @@ -219,7 +219,7 @@ void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ u32 *gpmc_config = NULL; - struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; + gpmc_cfg = (struct gpmc *)GPMC_BASE; u32 base = 0; u32 size = 0; u32 f_off = CONFIG_SYS_MONITOR_LEN; @@ -227,27 +227,26 @@ void gpmc_init(void) u32 config = 0;
/* global settings */ - writel(0, &gpmc_base->irqenable); /* isr's sources masked */ - writel(0, &gpmc_base->timeout_control);/* timeout disable */ + writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ + writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
- config = readl(&gpmc_base->config); + config = readl(&gpmc_cfg->config); config &= (~0xf00); - writel(config, &gpmc_base->config); + writel(config, &gpmc_cfg->config);
/* * Disable the GPMC0 config set by ROM code * It conflicts with our MPDB (both at 0x08000000) */ - writel(0, &gpmc_base->cs[0].config7); + writel(0, &gpmc_cfg->cs[0].config7); sdelay(1000);
#if defined(CONFIG_CMD_NAND) /* CS 0 */ gpmc_config = gpmc_m_nand; - gpmc_cfg = gpmc_base;
base = PISMO1_NAND_BASE; size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size); + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_NAND) f_off = SMNAND_ENV_OFFSET; f_sec = SZ_128K; @@ -263,7 +262,7 @@ void gpmc_init(void) gpmc_config = gpmc_onenand; base = PISMO1_ONEN_BASE; size = PISMO1_ONEN_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size); + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_ONENAND) f_off = ONENAND_ENV_OFFSET; f_sec = SZ_128K; diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index b18fea0..4ac58a8 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -32,7 +32,6 @@ #include <i2c.h>
extern omap3_sysinfo sysinfo; -static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; static char *rev_s[CPU_3XX_MAX_REV] = { @@ -160,7 +159,7 @@ u32 get_gpmc0_base(void) { u32 b;
- b = readl(&gpmc_base->cs[0].config7); + b = readl(&gpmc_cfg->cs[0].config7); b &= 0x1F; /* keep base [5:0] */ b = b << 24; /* ret 0x0b000000 */ return b; diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 89e8b1c..99b9cef 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -30,7 +30,6 @@ #include <nand.h>
static uint8_t cs; -static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
/* @@ -48,13 +47,13 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, */ switch (ctrl) { case NAND_CTRL_CHANGE | NAND_CTRL_CLE: - this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd; + this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; break; case NAND_CTRL_CHANGE | NAND_CTRL_ALE: - this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_adr; + this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; break; case NAND_CTRL_CHANGE | NAND_NCE: - this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_dat; + this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; break; }
@@ -74,8 +73,8 @@ static void omap_hwecc_init(struct nand_chip *chip) * Init ECC Control Register * Clear all ECC | Enable Reg1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control); - writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_base->ecc_size_config); + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config); }
/* @@ -178,7 +177,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, u_int32_t val;
/* Start Reading from HW ECC1_Result = 0x200 */ - val = readl(&gpmc_base->ecc1_result); + val = readl(&gpmc_cfg->ecc1_result);
ecc_code[0] = val & 0xFF; ecc_code[1] = (val >> 16) & 0xFF; @@ -188,7 +187,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, * Stop reading anymore ECC vals and clear old results * enable will be called if more reads are required */ - writel(0x000, &gpmc_base->ecc_config); + writel(0x000, &gpmc_cfg->ecc_config);
return 0; } @@ -207,7 +206,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) case NAND_ECC_READ: case NAND_ECC_WRITE: /* Clear the ecc result registers, select ecc reg as 1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control); + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
/* * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes @@ -215,9 +214,9 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) * we just have a single ECC engine for all CS */ writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, - &gpmc_base->ecc_size_config); + &gpmc_cfg->ecc_size_config); val = (dev_width << 7) | (cs << 1) | (0x1); - writel(val, &gpmc_base->ecc_config); + writel(val, &gpmc_cfg->ecc_config); break; default: printf("Error: Unrecognized Mode[%d]!\n", mode); @@ -311,7 +310,7 @@ int board_nand_init(struct nand_chip *nand) */ while (cs < GPMC_MAX_CS) { /* Check if NAND type is set */ - if ((readl(&gpmc_base->cs[cs].config1) & 0xC00) == 0x800) { + if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) { /* Found it!! */ break; } @@ -323,18 +322,18 @@ int board_nand_init(struct nand_chip *nand) return -ENODEV; }
- gpmc_config = readl(&gpmc_base->config); + gpmc_config = readl(&gpmc_cfg->config); /* Disable Write protect */ gpmc_config |= 0x10; - writel(gpmc_config, &gpmc_base->config); + writel(gpmc_config, &gpmc_cfg->config);
- nand->IO_ADDR_R = (void __iomem *)&gpmc_base->cs[cs].nand_dat; - nand->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd; + nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; + nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
nand->cmd_ctrl = omap_nand_hwcontrol; nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR; /* If we are 16 bit dev, our gpmc config tells us that */ - if ((readl(&gpmc_base->cs[cs].config1) & 0x3000) == 0x1000) + if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) nand->options |= NAND_BUSWIDTH_16;
nand->chip_delay = 100;