Hi,
On 01/16/2015 01:58 PM, Joonyoung Shim wrote:
Hi,
On 01/15/2015 10:31 PM, Akshay Saraswat wrote:
We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt values from a function refactored as per SoC versions. This patch adds support for fetching peripheral rates for Exynos5420 and Exynos5800.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com
Changes since v1:
- Changes suuport -> support in commit message.
- Removed position change of exynos5420_get_pll_clk.
- Removed #ifdef.
arch/arm/cpu/armv7/exynos/clock.c | 151 +++++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-exynos/clk.h | 5 +- 2 files changed, 148 insertions(+), 8 deletions(-)
[snip]
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..606b3ef 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -23,8 +23,9 @@ #define SET_RATIO(x, y) ((y & 0xf) << (x << 4))
enum pll_src_bit {
- EXYNOS_SRC_MPLL = 6,
- EXYNOS_SRC_EPLL,
- EXYNOS542x_SRC_MPLL = 3,
- EXYNOS_SRC_MPLL = EXYNOS542x_SRC_EPLL = 6,
- EXYNOS_SRC_EPLL = EXYNOS542x_SRC_RPLL, EXYNOS_SRC_VPLL,
};
CC arch/arm/cpu/armv7/exynos/clock.o In file included from arch/arm/cpu/armv7/exynos/clock.c:11:0: ./arch/arm/include/asm/arch/clk.h:27:20: error: ‘EXYNOS542x_SRC_EPLL’ undeclared here (not in a function) EXYNOS_SRC_MPLL = EXYNOS542x_SRC_EPLL = 6, ^ ./arch/arm/include/asm/arch/clk.h:28:20: error: ‘EXYNOS542x_SRC_RPLL’ undeclared here (not in a function) EXYNOS_SRC_EPLL = EXYNOS542x_SRC_RPLL, ^ make[2]: *** [arch/arm/cpu/armv7/exynos/clock.o] Error 1 make[1]: *** [arch/arm/cpu/armv7/exynos] Error 2 make: *** [arch/arm/cpu/armv7] Error 2
Thanks.
Could you use one item by one line like below?
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..da9bfcd 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -26,6 +26,9 @@ enum pll_src_bit { EXYNOS_SRC_MPLL = 6, EXYNOS_SRC_EPLL, EXYNOS_SRC_VPLL,
- EXYNOS542x_SRC_MPLL = 3,
- EXYNOS542x_SRC_EPLL = 6,
- EXYNOS542x_SRC_RPLL,
};
unsigned long get_pll_clk(int pllreg);
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