From: Wenyou Yang wenyou.yang@atmel.com
The SAMA5D27-SiP (System in Package) integrates the SAMA5D2 with 1Gbit DDR2-SDRAM in a single package.
The SAMA5D27 SOM1 embeds a 64Mbit QSPI flash, KSZ8081 Phy and Mac-address EEPROM.
Signed-off-by: Wenyou Yang wenyou.yang@microchip.com ---
Changes in v5: - Rebase the u-boot/master (8a33cb8b6bd). - Drop the applied patches.
Changes in v4: - Rebase the uboot/master (84a4206). - Remove the default config file for the spiflash. - Integrate the following patches into this patch series. 1./ [PATCH v2 0/3] board: atmel: Set the ethernet mac address from eeprom 2./ [PATCH 1/7] lib: at91: Add logo files used by API from DM_VIDEO 3./ [PATCH 2/7] atmel: common: Add function to display via DM_VIDEO's API 4./ [PATCH] board: sama5d2_xplained: Make SPL work on spiflash - Remove the dependency on [PATCH 0/5] configs: at91: Remove value of CONFIG_SYS_EXTRA_OPTIONS option.
Changes in v3: - Rebase on the PATCH: Atmel PIT timer driver and Remove CONFIG_SYS_EXTRA_OPTIONS. - Use the new Atmel PIT timer driver. - Remove "SAMA5D2" from CONFIG_SYS_EXTRA_OPTIONS options. - Move CONFIG_ENV_IS_IN_FAT to Kconfig.
Changes in v2: - Add the reviewed-by tag. - Add the help in Kconfig to describe the board and peripherals. - Add the code to display the company's logo and board information. - Replace the code to set the ethernet mac address with the common code from the board/atmel/common folder.
arch/arm/dts/Makefile | 3 + arch/arm/dts/at91-sama5d27_som1_ek.dts | 215 ++++++++++++++++++++++++ arch/arm/dts/sama5d2.dtsi | 20 +++ arch/arm/dts/sama5d27_som1.dtsi | 159 ++++++++++++++++++ arch/arm/mach-at91/Kconfig | 14 ++ board/atmel/sama5d27_som1_ek/Kconfig | 15 ++ board/atmel/sama5d27_som1_ek/MAINTAINERS | 6 + board/atmel/sama5d27_som1_ek/Makefile | 8 + board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 189 +++++++++++++++++++++ configs/sama5d27_som1_ek_mmc_defconfig | 88 ++++++++++ include/configs/sama5d27_som1_ek.h | 92 ++++++++++ 11 files changed, 809 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d27_som1_ek.dts create mode 100644 arch/arm/dts/sama5d27_som1.dtsi create mode 100644 board/atmel/sama5d27_som1_ek/Kconfig create mode 100644 board/atmel/sama5d27_som1_ek/MAINTAINERS create mode 100644 board/atmel/sama5d27_som1_ek/Makefile create mode 100644 board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c create mode 100644 configs/sama5d27_som1_ek_mmc_defconfig create mode 100644 include/configs/sama5d27_som1_ek.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 10d397d700..85ce68789a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -420,6 +420,9 @@ dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ at91-sama5d2_xplained.dtb
+dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \ + at91-sama5d27_som1_ek.dtb + dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ sama5d31ek.dtb \ sama5d33ek.dtb \ diff --git a/arch/arm/dts/at91-sama5d27_som1_ek.dts b/arch/arm/dts/at91-sama5d27_som1_ek.dts new file mode 100644 index 0000000000..5e62d4af71 --- /dev/null +++ b/arch/arm/dts/at91-sama5d27_som1_ek.dts @@ -0,0 +1,215 @@ +/* + * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27 SOM1 EK board + * + * Copyright (C) 2017 Microchip Corporation + * Wenyou Yang wenyou.yang@microchip.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "sama5d27_som1.dtsi" + +/ { + model = "Atmel SAMA5D27 SOM1 EK"; + compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d2", "atmel,sama5"; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart1; + }; + + ahb { + usb1: ohci@00400000 { + num-ports = <3>; + atmel,vbus-gpio = <&pioA 42 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; + }; + + usb2: ehci@00500000 { + status = "okay"; + }; + + sdmmc0: sdio-host@a0000000 { + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + sdmmc1: sdio-host@b0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + status = "okay"; /* conflict with qspi0 */ + u-boot,dm-pre-reloc; + }; + + apb { + hlcdc: hlcdc@f0000000 { + atmel,vl-bpix = <4>; + atmel,guard-time = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>; + status = "okay"; + u-boot,dm-pre-reloc; + + display-timings { + u-boot,dm-pre-reloc; + 480x272 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hsync-len = <41>; + hfront-porch = <2>; + hback-porch = <2>; + vfront-porch = <2>; + vback-porch = <2>; + vsync-len = <11>; + u-boot,dm-pre-reloc; + }; + }; + }; + + uart1: serial@f8020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + pioA: gpio@fc038000 { + pinctrl { + pinctrl_lcd_base: pinctrl_lcd_base { + pinmux = <PIN_PC5__LCDVSYNC>, + <PIN_PC6__LCDHSYNC>, + <PIN_PC8__LCDDEN>, + <PIN_PC7__LCDPCK>; + bias-disable; + }; + + pinctrl_lcd_pwm: pinctrl_lcd_pwm { + pinmux = <PIN_PC3__LCDPWM>; + bias-disable; + }; + + pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 { + pinmux = <PIN_PB13__LCDDAT2>, + <PIN_PB14__LCDDAT3>, + <PIN_PB15__LCDDAT4>, + <PIN_PB16__LCDDAT5>, + <PIN_PB17__LCDDAT6>, + <PIN_PB18__LCDDAT7>, + <PIN_PB21__LCDDAT10>, + <PIN_PB22__LCDDAT11>, + <PIN_PB23__LCDDAT12>, + <PIN_PB24__LCDDAT13>, + <PIN_PB25__LCDDAT14>, + <PIN_PB26__LCDDAT15>, + <PIN_PB29__LCDDAT18>, + <PIN_PB30__LCDDAT19>, + <PIN_PB31__LCDDAT20>, + <PIN_PC0__LCDDAT21>, + <PIN_PC1__LCDDAT22>, + <PIN_PC2__LCDDAT23>; + bias-disable; + }; + + pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA6__SDMMC0_DAT4>, + <PIN_PA7__SDMMC0_DAT5>, + <PIN_PA8__SDMMC0_DAT6>, + <PIN_PA9__SDMMC0_DAT7>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA10__SDMMC0_RSTN>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { + pinmux = <PIN_PA28__SDMMC1_CMD>, + <PIN_PA18__SDMMC1_DAT0>, + <PIN_PA19__SDMMC1_DAT1>, + <PIN_PA20__SDMMC1_DAT2>, + <PIN_PA21__SDMMC1_DAT3>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + pinmux = <PIN_PA22__SDMMC1_CK>, + <PIN_PA30__SDMMC1_CD>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_uart1_default: uart1_default { + pinmux = <PIN_PD2__URXD1>, + <PIN_PD3__UTXD1>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB10__GPIO>; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PA31__GPIO>; + bias-disable; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index d8a65145d6..2bcf1a1f7c 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -504,11 +504,13 @@ qspi0_clk: qspi0_clk@52 { #clock-cells = <0>; reg = <52>; + u-boot,dm-pre-reloc; };
qspi1_clk: qspi1_clk@53 { #clock-cells = <0>; reg = <53>; + u-boot,dm-pre-reloc; }; };
@@ -595,6 +597,16 @@ status = "disabled"; };
+ qspi1: spi@f0024000 { + compatible = "atmel,sama5d2-qspi"; + reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&qspi1_clk>; + status = "disabled"; + }; + spi0: spi@f8000000 { compatible = "atmel,at91rm9200-spi"; reg = <0xf8000000 0x100>; @@ -694,6 +706,14 @@ status = "disabled"; };
+ uart3: serial@fc008000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc008000 0x100>; + clocks = <&uart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + i2c1: i2c@fc028000 { compatible = "atmel,sama5d2-i2c"; reg = <0xfc028000 0x100>; diff --git a/arch/arm/dts/sama5d27_som1.dtsi b/arch/arm/dts/sama5d27_som1.dtsi new file mode 100644 index 0000000000..0c44a97f64 --- /dev/null +++ b/arch/arm/dts/sama5d27_som1.dtsi @@ -0,0 +1,159 @@ +/* + * sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SOM1 + * + * Copyright (C) 2017 Microchip Corporation + * Wenyou Yang wenyou.yang@microchip.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +/ { + model = "Atmel SAMA5D27 SOM1 EK"; + compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d2", "atmel,sama5"; + + memory { + reg = <0x20000000 0x8000000>; + }; + + aliases { + spi0 = &qspi1; + u-boot,dm-pre-reloc; + }; + + ahb { + apb { + qspi1: spi@f0024000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_sck_cs_default &pinctrl_qspi1_dat_default>; + status = "okay"; + u-boot,dm-pre-reloc; + + spi_flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + u-boot,dm-pre-reloc; + }; + }; + + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + }; + }; + + i2c0: i2c@f8028000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + status = "okay"; + + i2c_eeprom: i2c_eeprom@50 { + compatible = "microchip,24aa02e48"; + reg = <0x50>; + }; + }; + + i2c1: i2c@fc028000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + }; + + pioA: gpio@fc038000 { + pinctrl { + pinctrl_i2c0_default: i2c0_default { + pinmux = <PIN_PD21__TWD0>, + <PIN_PD22__TWCK0>; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD4__TWD1>, + <PIN_PD5__TWCK1>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PD31__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PD9__GTXCK>, + <PIN_PD10__GTXEN>, + <PIN_PD11__GRXDV>, + <PIN_PD12__GRXER>, + <PIN_PD13__GRX0>, + <PIN_PD14__GRX1>, + <PIN_PD15__GTX0>, + <PIN_PD16__GTX1>, + <PIN_PD17__GMDC>, + <PIN_PD18__GMDIO>; + bias-disable; + }; + + pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { + pinmux = <PIN_PB5__QSPI1_SCK>, + <PIN_PB6__QSPI1_CS>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_qspi1_dat_default: qspi1_dat_default { + pinmux = <PIN_PB7__QSPI1_IO0>, + <PIN_PB8__QSPI1_IO1>, + <PIN_PB9__QSPI1_IO2>, + <PIN_PB10__QSPI1_IO3>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 20f7eeaf09..a70b956fbc 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -99,6 +99,19 @@ config TARGET_SAMA5D2_XPLAINED select SUPPORT_SPL select BOARD_EARLY_INIT_F
+config TARGET_SAMA5D27_SOM1_EK + bool "SAMA5D27 SOM1 EK board" + select CPU_V7 + select SUPPORT_SPL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + help + The SAMA5D27 SOM1 embeds SAMA5D2 SiP(System in Package), + a 64Mbit QSPI flash, KSZ8081 Phy and a Mac-address EEPROM + 24AA02E48. The SAMA5D2 SiP integrates the ARM Cortex-A5 + processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM + in a single package. + config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" select CPU_V7 @@ -181,6 +194,7 @@ source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sama5d2_ptc/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" +source "board/atmel/sama5d27_som1_ek/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" diff --git a/board/atmel/sama5d27_som1_ek/Kconfig b/board/atmel/sama5d27_som1_ek/Kconfig new file mode 100644 index 0000000000..3276214d8c --- /dev/null +++ b/board/atmel/sama5d27_som1_ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D27_SOM1_EK + +config SYS_BOARD + default "sama5d27_som1_ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d27_som1_ek" + +endif diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS new file mode 100644 index 0000000000..609583c341 --- /dev/null +++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS @@ -0,0 +1,6 @@ +SAMA5D27 SOM1 EK BOARD +M: Wenyou Yang wenyou.yang@microchip.com +S: Maintained +F: board/atmel/sama5d27_som1_ek/ +F: include/configs/sama5d27_som1_ek.h +F: configs/sama5d27_som1_ek_mmc_defconfig diff --git a/board/atmel/sama5d27_som1_ek/Makefile b/board/atmel/sama5d27_som1_ek/Makefile new file mode 100644 index 0000000000..4ab242c4ac --- /dev/null +++ b/board/atmel/sama5d27_som1_ek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Microchip Corporation +# Wenyou Yang wenyou.yang@microchip.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d27_som1_ek.o diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c new file mode 100644 index 0000000000..80d772518d --- /dev/null +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2017 Microchip Corporation + * Wenyou.Yang wenyou.yang@microchip.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1); +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_DM_VIDEO + at91_video_show_board_info(); +#endif + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart1_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ + + at91_periph_clk_enable(ATMEL_ID_UART1); +} + +void board_debug_uart_init(void) +{ + board_uart1_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#define MAC24AA_MAC_OFFSET 0xfa + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(MAC24AA_MAC_OFFSET); +#endif + return 0; +} +#endif + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_ZQ_LONG | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->rtr = 0x511; + + ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + ddrc_conf(&ddrc_config); + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, + &mpddrc->rd_data_path); + + ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); + + writel(0x3, &mpddrc->cal_mr4); + writel(64, &mpddrc->tim_cal); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(40) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig new file mode 100644 index 0000000000..18d51131e6 --- /dev/null +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D27_SOM1_EK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xf8020000 +CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_ATMEL_USBA=y +CONFIG_DM_VIDEO=y +CONFIG_ATMEL_HLCD=y diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h new file mode 100644 index 0000000000..fdf19ad680 --- /dev/null +++ b/include/configs/sama5d27_som1_ek.h @@ -0,0 +1,92 @@ +/* + * Configuration file for the SAMA5D27 SOM1 EK Board. + * + * Copyright (C) 2017 Microchip Corporation + * Wenyou Yang wenyou.yang@microchip.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_TEXT_BASE +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_TEXT_BASE 0x23f00000 +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +#define CONFIG_MISC_INIT_R + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x8000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +/* SPI flash */ +#define CONFIG_SF_DEFAULT_SPEED 66000000 + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_SD_BOOT +/* u-boot env in sd/mmc card */ +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d27_som1_ek.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +#endif + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_OFFSET 0xb0000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0xc0000 0x20000; " \ + "sf read 0x22000000 0xe0000 0x400000; " \ + "bootz 0x22000000 - 0x21000000" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +#endif + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 +#endif + +#endif