This path add a new helper allowing to prefetch and lock instructions into cache. This is useful very early in the boot when no RAM is available yet.
Signed-off-by: Gregory CLEMENT gregory.clement@bootlin.com --- arch/mips/include/asm/cacheops.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 3161875441..98b67ccc8e 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void *addr) #endif }
+#define MIPS32_WHICH_ICACHE 0x0 +#define MIPS32_FETCH_AND_LOCK 0x7 + +#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2)) + +/* Prefetch and lock instructions into cache */ +static inline void icache_lock(void *func, size_t len) +{ + int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1; + + for (i = 0; i < lines; i++) { + asm volatile (" cache %0, %1(%2)" + : /* No Output */ + : "I" ICACHE_LOAD_LOCK, + "n" (i * ARCH_DMA_MINALIGN), + "r" (func) + : /* No Clobbers */); + } +} #endif /* !__ASSEMBLY__ */
/*