This patch adds Extricom EXSW6000 board, which is based on the Freescale 85xx core.
due to size limit it is sagmented to two.
on top of that, this patch is not complete without: Altera Stratix II, fpga loadi, and ndelay patches. Without them it will not compile. All three posted just before this post.
Signed-off-by: Eran Liberty eran.liberty@gmail.com
Index: CREDITS =================================================================== --- CREDITS (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 69) +++ CREDITS (.../branches/exsw6000) (revision 69) @@ -479,3 +479,8 @@ E: monstr@monstr.eu D: Support for Microblaze, ML401, XUPV2P board W: www.monstr.eu + +N: Eran Liberty +E: liberty@extricom.com +D: Support for Extricom, EXSW6000 board +W: www.extricom.com Index: include/configs/EXSW6000.h =================================================================== --- include/configs/EXSW6000.h (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ include/configs/EXSW6000.h (.../branches/exsw6000) (revision 69) @@ -0,0 +1,487 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom, eran.liberty@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 /* MPC8548 specific */ +#define CONFIG_EXSW6000 1 /* Extricom EXSW6000 (mega switch) board specific */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the CDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH +#define CONFIG_FORCE_FLASH_BANK_SIZE 0x800000 + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ + +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ + +#define CFG_BR0_PRELIM 0xff801001 +#define CFG_BR1_PRELIM 0xff001001 + +#define CFG_OR0_PRELIM 0xff806e65 +#define CFG_OR1_PRELIM 0xff806e65 + +#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ /* FIXME... understand y it makes a diffrernce to romove me */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (5000 << 10) /* 5MB Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8548@0" +#define OF_SOC "soc8548@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_85XX_PCI2 + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +#define CONFIG_FPGA (CFG_ALTERA_STRATIX_II) +#define CONFIG_MISC_INIT_R /* enable misc initialization including fpga */ +#define CONFIG_FPGA_BASE 0xF8000000 +#define CFG_BR3_PRELIM 0xf8001001 +#define CFG_OR3_PRELIM 0xfff00ff7 + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_FPGA \ + | CFG_CMD_MII ) +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (0x10 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * Reset Method + */ +#define CONFIG_RESET_RSCTR 1 + +#define CONFIG_BZIP2 1 + +#define CONFIG_LAST_STAGE_INIT + +/* + * Exteran Switch detection + */ +#undef CONFIG_EXSW0 /*8 */ +#undef CONFIG_EXSW1 /*9 */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#endif + +#define CONFIG_IPADDR ip_addr + +#define CONFIG_HOSTNAME exsw6000 +#define CONFIG_ROOTPATH nfs_root_fs_path +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP server_ip +#define CONFIG_GATEWAYIP gateway_ip +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=600000\0" \ + "ramdiskfile=ramfs.uboot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=exsw6000.btb\0" \ + "fpga_loadaddr=ff000000\0" \ + "fpga_dev=0\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ Index: Makefile =================================================================== --- Makefile (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 69) +++ Makefile (.../branches/exsw6000) (revision 69) @@ -1769,6 +1769,9 @@ MPC8548CDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds
+EXSW6000_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx exsw6000 extricom + MPC8555CDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds
Index: board/extricom/exsw6000/config.mk =================================================================== --- board/extricom/exsw6000/config.mk (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/config.mk (.../branches/exsw6000) (revision 69) @@ -0,0 +1,36 @@ +# (C) Copyright 2007 +# Eran Liberty, Extricom, eran.liberty@gmail.com. +# +# (C)Copyright 2004 +# Freescale Semiconductor. +# + +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Extricom EXSW6000 (codename Megaswitch) board +# + +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 +PLATFORM_CPPFLAGS += -DCONFIG_EXSW6000=1 Index: board/extricom/exsw6000/Makefile =================================================================== --- board/extricom/exsw6000/Makefile (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/Makefile (.../branches/exsw6000) (revision 69) @@ -0,0 +1,63 @@ +# (C) Copyright 2007 +# Eran Liberty, Extricom, eran.liberty@gmail.com +# +# (C) Copyright 2004 +# Freescale Semiconductor. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../../cds/common) +endif + +LIB = $(obj)lib$(BOARD).a + +# FIXME: look up eeprom & via and decide if they should stay or go +COBJS := $(BOARD).o \ + ft_board.o \ + fpga.o \ + +SOBJS := init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### Index: board/extricom/exsw6000/exsw6000.c =================================================================== --- board/extricom/exsw6000/exsw6000.c (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/exsw6000.c (.../branches/exsw6000) (revision 69) @@ -0,0 +1,424 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom, eran.liberty@gmail.com + * + * (C) Copyright 2004 + * Freescale Semiconductor. + * + * (C) Copyright 2002 + * Scott McNutt smcnutt@artesyncp.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <spd.h> +#include <miiphy.h> +#include <../drivers/tsec.h> +#include "fpga.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc (unsigned int dram_size); +#endif + +extern long int spd_sdram (void); + +void local_bus_init (void); +void sdram_init (void); + +int board_early_init_f (void) +{ + /* 0. Add TLB1 entry for FPGA accesss */ + mtspr (MAS0, TLB1_MAS0 (1, 7, 0)); + mtspr (MAS1, TLB1_MAS1 (1, 1, 0, 0, BOOKE_PAGESZ_1K)); + mtspr (MAS2, + TLB1_MAS2 (E500_TLB_EPN (CONFIG_FPGA_BASE), 0, 0, 0, 1, 1, 0, 1, + 0)); + mtspr (MAS3, + TLB1_MAS3 (E500_TLB_RPN (CONFIG_FPGA_BASE), 0, 0, 0, 0, 0, 1, 0, + 1, 0, 1)); + __asm__ __volatile__ ("isync;msync;tlbwe;isync"); + return 0; +} + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ + uint pci1_speed = CONFIG_SYS_CLK_FREQ; + + printf ("Board: EXSW6000\n"); + printf (" PCI1: %d bit, %s MHz, %s\n", + (pci1_32) ? 32 : 64, + (pci1_speed == 33000000) ? "33" : + (pci1_speed == 66000000) ? "66" : "unknown", + pci1_clk_sel ? "sync" : "async"); + + /* + * Initialize local bus. + */ + local_bus_init (); + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + + return 0; +} + +long int initdram (int board_type) +{ + long dram_size = 0; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + puts ("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur = &immap->im_gur; + + gur->ddrdllcr = 0x81000000; + asm ("sync;isync;msync"); + udelay (200); + } +#endif + dram_size = spd_sdram (); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc (dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init (); + + puts (" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void local_bus_init (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + get_sys_info (&sysinfo); + clkdiv = (lbc->lcrr & 0x0f) * 2; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + gur->lbiuiplldcr1 = 0x00078080; + if (clkdiv == 16) { + gur->lbiuiplldcr0 = 0x7c0f1bf0; + } else if (clkdiv == 8) { + gur->lbiuiplldcr0 = 0x6c0f1bf0; + } else if (clkdiv == 4) { + gur->lbiuiplldcr0 = 0x5c0f1bf0; + } + + lbc->lcrr |= 0x00030000; + + asm ("sync;isync;msync"); +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void sdram_init (void) +{ +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + /* FIXME: remove clenaly */ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + lbc->lbcr = CFG_LBC_LBCR; + asm ("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm ("msync"); +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf ("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, CFG_MEMTEST_END); + + printf ("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. + */ +void dummy_func (struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *tab) +{ +} + +static struct pci_config_table pci_exsw6000_config_table[] = { + {0x1556, 0x5555, + PCI_ANY_ID, + 0, + 0xd, + 0, + dummy_func, + {0, 0, 0}}, +}; + +static struct pci_controller hose[] = { + {config_table:pci_exsw6000_config_table,}, +}; + +#endif /* CONFIG_PCI */ + +void pci_init_board (void) +{ +#ifdef CONFIG_PCI + pci_mpc85xx_init ((struct pci_controller *)(&hose)); +#endif +} + +extern int fpga_loadi (int devnum, void *buf); +extern int Exsw6000_stratixII_fpp_pre_fn (int cookie); +extern int Exsw6000_stratixII_fpp_done_fn (int cookie); +extern int Exsw6000_stratixII_fpp_post_fn (int cookie); + +int misc_init_r (void) +{ + char *s; + ulong addr; + int devnum; + int conf_done; + + exsw6000_fpga_init (); + + /* if we have an enviroment fpga_image_addr */ + if ((s = getenv ("fpga_loadaddr")) != NULL) { + addr = simple_strtoul (s, NULL, 16); + if ((s = getenv ("fpga_dev")) != NULL) { + devnum = simple_strtoul (s, NULL, 16); + + Exsw6000_stratixII_fpp_pre_fn (0); + conf_done = Exsw6000_stratixII_fpp_done_fn (0); + Exsw6000_stratixII_fpp_post_fn (0); + if (!conf_done) { + printf ("FPGA loading\n"); + fpga_loadi (devnum, (void *)(addr)); + + /* FIXME make pci work with no re-reset */ + + } else { + printf ("FPGA already loaded\n"); + } + } + } + return 0; +} + +DECLARE_GLOBAL_DATA_PTR; + +extern int tsec_initialize (bd_t *, int, char *); + +#define MDPHY_MASK 0x3FE0 + +int is_connected (int addr1, int addr2) +{ + u16 dev1_ed_save; + u16 data; + char *devname = "exsw6000\0"; + int retval; + u16 test_vals[] = { 0x00e1, 0x0161, 0x01A1 }; + int i; + int timeout; + + /* save current value */ + if (miiphy_read (devname, addr1, 4, &data) != 0) { + printf ("Error reading from addr1 4\n"); + return -1; + } + dev1_ed_save = data; + + printf ("Detecting External switch."); + retval = 0; + for (i = 0; i < sizeof (test_vals) / sizeof (test_vals[0]); i++) { + if (miiphy_write (devname, addr1, 4, test_vals[i]) != 0) { + printf ("Error writing to addr1 4\n"); + return -1; + } + if (miiphy_read (devname, addr1, 0, &data) != 0) { + printf ("Error reading from addr1 0\n"); + return -1; + } + data |= PHY_BMCR_RST_NEG; + if (miiphy_write (devname, addr1, 0, data) != 0) { + printf ("Error writing to addr1 0\n"); + return -1; + } + data = 0; + timeout = 100000; + while (miiphy_read (devname, addr1, 1, &data) == 0 && + (data & PHY_BMSR_AUTN_COMP) == 0 && timeout--) { + if ((timeout % 10000) == 0) + printf ("."); + } + if (timeout == 0 || miiphy_read (devname, addr1, 1, &data) != 0) { + printf ("!"); + retval = 1; + break; + } + if (miiphy_read (devname, addr2, 5, &data) != 0) { + printf ("Error reading from addr2 5\n"); + return -1; + } + if ((data & MDPHY_MASK) != (test_vals[i] & MDPHY_MASK)) { + retval = 1; + break; + } + } + + /* reset saved value */ + if (miiphy_write (devname, addr1, 4, dev1_ed_save) != 0) { + printf ("Error writing to addr1 4\n"); + return -1; + } + if (miiphy_read (devname, addr1, 0, &data) != 0) { + printf ("Error reading from addr1 0\n"); + return -1; + } + data |= PHY_BMCR_RST_NEG; + if (miiphy_write (devname, addr1, 0, data) != 0) { + printf ("Error writing to addr1 0\n"); + return -1; + } + data = 0; + while (data & PHY_BMSR_AUTN_COMP) { + if (miiphy_write (devname, addr1, 1, data) != 0) { + printf ("Error writing to addr1 0\n"); + return -1; + } + } + if (retval == 1) { + printf (" not found\n"); + } else { + printf (" found.\n"); + } + return retval; +} + +/* we steel tsec.c private structure in order to use its function functions */ +struct tsec_info_struct { + unsigned int phyaddr; + u32 flags; + unsigned int phyregidx; +}; +extern void write_phy_reg (struct tsec_private *priv, uint regnum, uint value); +extern uint read_phy_reg (struct tsec_private *priv, uint regnum); + +static int exsw6000_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + struct tsec_private priv; + priv.phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR); + priv.phyaddr = addr; + *value = (unsigned short)read_phy_reg (&priv, reg); + return 0; +} +static int exsw6000_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct tsec_private priv; + priv.phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR); + priv.phyaddr = addr; + write_phy_reg (&priv, reg, value); + return 0; +} + +int last_stage_init (void) +{ + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register ("exsw6000", exsw6000_miiphy_read, + exsw6000_miiphy_write); +#endif + +#if defined(CONFIG_EXSW0) && defined(CONFIG_EXSW1) + /* Try to detect loopback as switch indicators */ + if (is_connected (CONFIG_EXSW0, CONFIG_EXSW1) == 0) { + printf ("Extranl Switch detected\n"); + } else { + printf ("no extranal switch\n"); + } +#endif + return 0; +}