As noticed while working on the USB xHCI support, Octeon needs to flush all pending writes so that the values are present in the memory. Add this "syncw" instruction (twice) to flush_dcache_range().
Signed-off-by: Stefan Roese sr@denx.de ---
(no changes since v1)
arch/mips/mach-octeon/cache.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c index 9a88bb97c7..f293d65dae 100644 --- a/arch/mips/mach-octeon/cache.c +++ b/arch/mips/mach-octeon/cache.c @@ -5,14 +5,13 @@
#include <cpu_func.h>
-/* - * The Octeon platform is cache coherent and cache flushes and invalidates - * are not needed. Define some platform specific empty flush_foo() - * functions here to overwrite the _weak common function as a no-op. - * This effectively disables all cache operations. - */ +/* Octeon memory write barrier */ +#define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : : "memory") + void flush_dcache_range(ulong start_addr, ulong stop) { + /* Flush all pending writes */ + CVMX_SYNCW; }
void flush_cache(ulong start_addr, ulong size) @@ -21,4 +20,5 @@ void flush_cache(ulong start_addr, ulong size)
void invalidate_dcache_range(ulong start_addr, ulong stop) { + /* Don't need to do anything for OCTEON */ }