[U-Boot] [PATCH 1/2 V2] cmd_i2c: rename EDO, DDR and SDRAM to avoid conflict with at91 memory setup

17 Dec 2008

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com
---
 common/cmd_i2c.c |   58 ++++++++++++++++++++++++++---------------------------
 1 files changed, 28 insertions(+), 30 deletions(-)

diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 448f2fe..9f7a1ea 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -712,7 +712,7 @@ static void decode_bits (u_char const b, char const *str[], int const do_once)
  */
 int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	enum { unknown, EDO, SDRAM, DDR2 } type;
+	enum { unknown, edo, sdram, ddr2 } type;
u_char	chip;
    u_char	data[128];
@@ -793,15 +793,15 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    puts ("Memory type                  ");
    switch (data[2]) {
    case 2:
-		type = EDO;
+		type = edo;
    	puts ("EDO\n");
    	break;
    case 4:
-		type = SDRAM;
+		type = sdram;
    	puts ("SDRAM\n");
    	break;
    case 8:
-		type = DDR2;
+		type = ddr2;
    	puts ("DDR2\n");
    	break;
    default:
@@ -823,7 +823,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    	printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("Number of ranks              %d\n",
    		(data[5] & 0x07) + 1);
    	break;
@@ -833,7 +833,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("Module data width            %d bits\n", data[6]);
    	break;
    default:
@@ -854,7 +854,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("SDRAM cycle time             ");
    	print_ddr2_tcyc (data[9]);
    	break;
@@ -865,7 +865,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("SDRAM access time            0.%d%d ns\n",
    		(data[10] >> 4) & 0x0F, data[10] & 0x0F);
    	break;
@@ -899,7 +899,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("SDRAM width (primary)        %d\n", data[13]);
    	break;
    default:
@@ -912,7 +912,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	if (data[14] != 0)
    		printf ("EDC width                    %d\n", data[14]);
    	break;
@@ -929,7 +929,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    	break;
    }
-	if (DDR2 != type) {
+	if (type != ddr2) {
    	printf ("Min clock delay, back-to-back random column addresses "
    		"%d\n", data[15]);
    }
@@ -944,7 +944,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    printf ("Number of banks              %d\n", data[17]);
switch (type) {
-	case DDR2:
+	case ddr2:
    	puts ("CAS latency(s)              ");
    	decode_bits (data[18], decode_CAS_DDR2, 0);
    	putc ('\n');
@@ -956,20 +956,18 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    	break;
    }
-	if (DDR2 != type) {
+	if (type != ddr2) {
    	puts ("CS latency(s)               ");
    	decode_bits (data[19], decode_CS_WE_default, 0);
    	putc ('\n');
-	}
-	if (DDR2 != type) {
    	puts ("WE latency(s)               ");
    	decode_bits (data[20], decode_CS_WE_default, 0);
    	putc ('\n');
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	puts ("Module attributes:\n");
    	if (data[21] & 0x80)
    		puts ("  TBD (bit 7)\n");
@@ -995,7 +993,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	decode_bits (data[22], decode_byte22_DDR2, 0);
    	break;
    default:
@@ -1014,7 +1012,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("SDRAM cycle time (2nd highest CAS latency)        ");
    	print_ddr2_tcyc (data[23]);
    	break;
@@ -1025,7 +1023,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("SDRAM access from clock (2nd highest CAS latency) 0."
    		"%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
    	break;
@@ -1036,7 +1034,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("SDRAM cycle time (3rd highest CAS latency)        ");
    	print_ddr2_tcyc (data[25]);
    	break;
@@ -1047,7 +1045,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("SDRAM access from clock (3rd highest CAS latency) 0."
    		"%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
    	break;
@@ -1058,7 +1056,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("Minimum row precharge        %d.%02d ns\n",
    		(data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
    	break;
@@ -1068,7 +1066,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("Row active to row active min %d.%02d ns\n",
    		(data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
    	break;
@@ -1078,7 +1076,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("RAS to CAS delay min         %d.%02d ns\n",
    		(data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
    	break;
@@ -1090,7 +1088,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    printf ("Minimum RAS pulse width      %d ns\n", data[30]);
switch (type) {
-	case DDR2:
+	case ddr2:
    	puts ("Density of each row          ");
    	decode_bits (data[31], decode_row_density_DDR2, 1);
    	putc ('\n');
@@ -1103,7 +1101,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	puts ("Command and Address setup    ");
    	if (data[32] >= 0xA0) {
    		printf ("1.%d%d ns\n",
@@ -1121,7 +1119,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	puts ("Command and Address hold     ");
    	if (data[33] >= 0xA0) {
    		printf ("1.%d%d ns\n",
@@ -1139,7 +1137,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("Data signal input setup      0.%d%d ns\n",
    		(data[34] >> 4) & 0x0F, data[34] & 0x0F);
    	break;
@@ -1151,7 +1149,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    }
switch (type) {
-	case DDR2:
+	case ddr2:
    	printf ("Data signal input hold       0.%d%d ns\n",
    		(data[35] >> 4) & 0x0F, data[35] & 0x0F);
    	break;
@@ -1178,7 +1176,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
    	printf ("%02X ", data[j]);
    putc ('\n');
-	if (DDR2 != type) {
+	if (type != ddr2) {
    	printf ("Speed rating                 PC%d\n",
    		data[126] == 0x66 ? 66 : data[126]);
    }
-- 
1.5.6.5


    